Functions
CSL_TAC_BE_FUNCTION

Functions

void CSL_TAC_BETI_enable ()
void CSL_TAC_BETI_disable ()
CSL_TAC_BETI_enableStatus CSL_TAC_BETI_getEnableStatus ()
void CSL_TAC_BETI_getStatus (CSL_TAC_BETI_status *betiStatus)
void CSL_TAC_BETI_setWatchDog (Uint16 reloadCnt)
Uint16 CSL_TAC_BETI_getWatchDogStatus ()
CSL_TAC_BETI_wdInterruptStatus CSL_TAC_BETI_getWatchDogInterruptStatus ()
void CSL_TAC_BETI_clearWatchDogInterrupt ()
void CSL_TAC_BEII_enable ()
void CSL_TAC_BEII_disable ()
CSL_TAC_BEII_enableStatus CSL_TAC_BEII_getEnableStatus ()
void CSL_TAC_BEII_getInterruptStatus (CSL_TAC_BEII_interruptStatus *interruptStatus)
void CSL_TAC_BEII_getEnabledInterruptStatus (CSL_TAC_BEII_interruptStatus *interruptEnStatus)
void CSL_TAC_BEII_forceInterrupts (CSL_TAC_BEII_interruptStatus *interruptsToForce)
void CSL_TAC_BEII_clearInterrupts (CSL_TAC_BEII_interruptStatus *interruptsToClear)
void CSL_TAC_BEII_enableInterrupts (CSL_TAC_BEII_interruptStatus *interruptsToEnable)
void CSL_TAC_BEII_disableInterrupts (CSL_TAC_BEII_interruptStatus *interruptsToDisable)
void CSL_TAC_BEII_setEOI (Uint32 eoiVecValue)
Uint32 CSL_TAC_BEII_getEOI ()
CSL_TAC_BE_strmPwrMeasMode CSL_TAC_BE_getStrmPwrMeasMode ()
void CSL_TAC_BE_setSwIterStart ()
void CSL_TAC_BE_setTimestamp (CSL_TAC_BE_Timestamp_req *timestamp)
void CSL_TAC_BE_getTimestamp (CSL_TAC_BE_Timestamp_req *timestamp)

Function Documentation

CSL_TAC_BE_strmPwrMeasMode CSL_TAC_BE_getStrmPwrMeasMode ( )


CSL_TAC_BE_getStrmPwrMeasMode

Description
This function returns the accumulation mode used for the stream power measurement.

Arguments

    None
    

Return Value
CSL_TAC_BE_strmPwrMeasMode_SlotMode The accumulation length is 1 slot (2560 chips)
CSL_TAC_BE_strmPwrMeasMode_SymbolMode The accumulation length is 1 symbol (256 chips)

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BETI_SPC_ACC_MODE

Example

    CSL_TAC_BE_strmPwrMeasMode measMode;

    measMode = CSL_TAC_BE_getStrmPwrMeasMode();
    
void CSL_TAC_BE_getTimestamp ( CSL_TAC_BE_Timestamp_req *  timestamp)


CSL_TAC_BE_getTimestamp

Description
This function reads the Back End Timestamp register.

Arguments

    timestamp       Structure with timestamp parameters.
    

Return Value
None

Pre Condition
None

Post Condition
None

Reads
TAC_DATA_BE_TIME_CHIP, TAC_DATA_BE_TIME_SLOT, TAC_DATA_BE_TIME_FRAME

Example

    CSL_TAC_BE_Timestamp_req   timestamp;

    CSL_TAC_BE_getTimestamp(&timestamp);
    


CSL_TAC_BE_setSwIterStart

Description
This function enables the Software to bypass the HW iteration start line and triggers one iteration processing on each SGCP.

This function should be used only for debugging purposes.

Arguments

    None
    

Return Value
None

Pre Condition
None

Post Condition
The HW iteration start line is bypassed. After this point the iteration processing can be triggered only by subsequent calls to CSL_TAC_BE_setSwIterStart() API.

To take the HW out of this mode the application needs to issue a a device reset using CSL_TAC_FE_softwareReset() API.

Writes
TAC_CFG_BETI_SW_ITE_START_ITE_START=1

Example

    CSL_TAC_BE_Timestamp_req   timestamp;
    Uint16  frame = 0;
    Uint16  chip  = 0;
    Uint8   slot  = 0;
    Uint16  numIter;

    // Repeat for 640 iterations
    for (numIter = 0; numIter < 640; numIter++)
    {
        // Set the time stamp in the HW
        timestamp.chipId  = chip;
        timestamp.slotId  = slot;
        timestamp.frameId = frame;

        CSL_TAC_BE_setTimestamp(&timestamp);

        // Trigger 1 iteration worth of processing
        CSL_TAC_BE_setSwIterStart();

        ...
        // Increment the chip by 1 iteration (i.e. 4 chips)
        chip += 4;

        // Check for the slot boundary
        if (chip == 2560)
        {
            // Check for the frame boundary
            if (++slot == 15)
            {
                slot = 0;

                // Check for the super frame wrap
                frame = (frame + 1) & 4095;
            }
        }
    }
    
void CSL_TAC_BE_setTimestamp ( CSL_TAC_BE_Timestamp_req *  timestamp)


CSL_TAC_BE_setTimestamp

Description
This function configures the Back End Timestamp register.

Arguments

    timestamp       Structure with timestamp parameters.
    

Return Value
None

Pre Condition
None

Post Condition
The Back-End Timestamp register is set.

Writes
TAC_DATA_BE_TIME_CHIP, TAC_DATA_BE_TIME_SLOT, TAC_DATA_BE_TIME_FRAME

Example

    CSL_TAC_BE_Timestamp_req   timestamp;

    timestamp.chipId  = 8;
    timestamp.slotId  = 3;
    timestamp.frameId = 6;

    CSL_TAC_BE_setTimestamp(&timestamp);
    
void CSL_TAC_BEII_clearInterrupts ( CSL_TAC_BEII_interruptStatus *  interruptsToClear)


CSL_TAC_BEII_clearInterrupts

Description
This function clears the BEII Interrupts

Arguments

    interruptsToClear Structure with the BETI interrupts to clear. A given
                      interrupt will be cleared if the corresponding flag
                      is set to 1.
    

Return Value
None

Pre Condition
None

Post Condition
The interrupts specified in the interruptsToClear structure are cleared.

Writes
TAC_CFG_BEII_ICS0_SGCP0_CYC_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP0_FIFO_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP0_SEQ_CLR, TAC_CFG_BEII_ICS0_SGCP0_IB_WR_MISS_CLR, TAC_CFG_BEII_ICS0_SGCP1_CYC_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP1_FIFO_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP1_SEQ_CLR, TAC_CFG_BEII_ICS0_SGCP1_IB_WR_MISS_CLR, TAC_CFG_BEII_ICS0_SGCP2_CYC_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP2_FIFO_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP2_SEQ_CLR, TAC_CFG_BEII_ICS0_SGCP2_IB_WR_MISS_CLR, TAC_CFG_BEII_ICS0_SGCP3_CYC_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP3_FIFO_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP3_SEQ_CLR, TAC_CFG_BEII_ICS0_SGCP3_IB_WR_MISS_CLR, TAC_CFG_BEII_ICS0_SGCP4_CYC_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP4_FIFO_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP4_SEQ_CLR, TAC_CFG_BEII_ICS0_SGCP4_IB_WR_MISS_CLR, TAC_CFG_BEII_ICS0_SGCP5_CYC_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP5_FIFO_OVER_CLR, TAC_CFG_BEII_ICS0_SGCP5_SEQ_CLR, TAC_CFG_BEII_ICS0_SGCP5_IB_WR_MISS_CLR, TAC_CFG_BEII_ICS1_FE0_TRANS_CLR, TAC_CFG_BEII_ICS1_FE1_TRANS_CLR, TAC_CFG_BEII_ICS1_FE2_TRANS_CLR, TAC_CFG_BEII_ICS1_BE_WD_CLR

Affects
TAC_CFG_BEII_IRS0_SGCP0_CYC_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP0_FIFO_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP0_SEQ_STAT = 0, TAC_CFG_BEII_IRS0_SGCP0_IB_WR_MISS_STAT = 0, TAC_CFG_BEII_IRS0_SGCP1_CYC_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP1_FIFO_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP1_SEQ_STAT = 0, TAC_CFG_BEII_IRS0_SGCP1_IB_WR_MISS_STAT = 0, TAC_CFG_BEII_IRS0_SGCP2_CYC_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP2_FIFO_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP2_SEQ_STAT = 0, TAC_CFG_BEII_IRS0_SGCP2_IB_WR_MISS_STAT = 0, TAC_CFG_BEII_IRS0_SGCP3_CYC_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP3_FIFO_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP3_SEQ_STAT = 0, TAC_CFG_BEII_IRS0_SGCP3_IB_WR_MISS_STAT = 0, TAC_CFG_BEII_IRS0_SGCP4_CYC_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP4_FIFO_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP4_SEQ_STAT = 0, TAC_CFG_BEII_IRS0_SGCP4_IB_WR_MISS_STAT = 0, TAC_CFG_BEII_IRS0_SGCP5_CYC_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP5_FIFO_OVER_STAT = 0, TAC_CFG_BEII_IRS0_SGCP5_SEQ_STAT = 0, TAC_CFG_BEII_IRS0_SGCP5_IB_WR_MISS_STAT = 0, TAC_CFG_BEII_IRS1_FE0_TRANS_STAT = 0, TAC_CFG_BEII_IRS1_FE1_TRANS_STAT = 0, TAC_CFG_BEII_IRS1_FE2_TRANS_STAT = 0, TAC_CFG_BEII_IRS1_BE_WD_STAT = 0

Example

    CSL_TAC_BEII_interruptStatus  interruptStatus;

    // Get the current interrupt status
    CSL_TAC_BEII_getInterruptStatus(&interruptStatus);

    // Clear all the interrupts that have occured
    CSL_TAC_BEII_clearInterrupts(&interruptStatus);
    


CSL_TAC_BEII_clearInterrupts

Description
This function clears the BEII Interrupts

Arguments

    interruptsToClear Structure with the BETI interrupts to clear. A given
                      interrupt will be cleared if the corresponding flag
                      is set to 1.
    

Return Value
None

Pre Condition
None

Post Condition
The interrupts specified in the interruptsToClear structure are cleared.

Writes
TAC_CFG_BEII_ICS_0_SGCP0_CYC_OVER_CLR, TAC_CFG_BEII_ICS_0_SGCP0_FIFO_OVER_CLR, TAC_CFG_BEII_ICS_0_SGCP0_SEQ_CLR, TAC_CFG_BEII_ICS_0_SGCP0_IB_WR_MISS_CLR, TAC_CFG_BEII_ICS_0_SGCP1_CYC_OVER_CLR, TAC_CFG_BEII_ICS_0_SGCP1_FIFO_OVER_CLR, TAC_CFG_BEII_ICS_0_SGCP1_SEQ_CLR, TAC_CFG_BEII_ICS_0_SGCP1_IB_WR_MISS_CLR, TAC_CFG_BEII_ICS_1_FE0_TRANS_CLR, TAC_CFG_BEII_ICS_1_BE_WD_CLR

Affects
TAC_CFG_BEII_IRS_0_SGCP0_CYC_OVER_STAT = 0, TAC_CFG_BEII_IRS_0_SGCP0_FIFO_OVER_STAT = 0, TAC_CFG_BEII_IRS_0_SGCP0_SEQ_STAT = 0, TAC_CFG_BEII_IRS_0_SGCP0_IB_WR_MISS_STAT = 0, TAC_CFG_BEII_IRS_0_SGCP1_CYC_OVER_STAT = 0, TAC_CFG_BEII_IRS_0_SGCP1_FIFO_OVER_STAT = 0, TAC_CFG_BEII_IRS_0_SGCP1_SEQ_STAT = 0, TAC_CFG_BEII_IRS_0_SGCP1_IB_WR_MISS_STAT = 0, TAC_CFG_BEII_IRS_1_FE0_TRANS_STAT = 0, TAC_CFG_BEII_IRS_1_BE_WD_STAT = 0

Example

    CSL_TAC_BEII_interruptStatus  interruptStatus;

    // Get the current interrupt status
    CSL_TAC_BEII_getInterruptStatus(&interruptStatus);

    // Clear all the interrupts that have occured
    CSL_TAC_BEII_clearInterrupts(&interruptStatus);
    


CSL_TAC_BEII_disable

Description
This function disables the TAC2 Back End Interrupt Interface (BEII)

Arguments

    None
    

Return Value
None

Pre Condition
None

Post Condition
The Back End Interrupt Interface is disabled.

Writes
TAC_CFG_BEII_CTRL_ENABLE=0

Example

    CSL_TAC_BEII_disable();
    
void CSL_TAC_BEII_disableInterrupts ( CSL_TAC_BEII_interruptStatus *  interruptsToDisable)


CSL_TAC_BEII_disableInterrupts

Description
This function disables the BEII Interrupts

Arguments

    interruptsToEnable Structure with the BETI interrupts to disable. A given
                       interrupt will be disabled if the corresponding flag is
                       set to 1.
    

Return Value
None

Pre Condition
None

Post Condition
The interrupts specified in the interruptsToDisable structure are disabled.

Writes
TAC_CFG_BEII_IECS0_SGCP0_CYC_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP0_FIFO_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP0_SEQ_CLEAR, TAC_CFG_BEII_IECS0_SGCP0_IB_WR_MISS_CLEAR, TAC_CFG_BEII_IECS0_SGCP1_CYC_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP1_FIFO_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP1_SEQ_CLEAR, TAC_CFG_BEII_IECS0_SGCP1_IB_WR_MISS_CLEAR, TAC_CFG_BEII_IECS0_SGCP2_CYC_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP2_FIFO_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP2_SEQ_CLEAR, TAC_CFG_BEII_IECS0_SGCP2_IB_WR_MISS_CLEAR, TAC_CFG_BEII_IECS0_SGCP3_CYC_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP3_FIFO_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP3_SEQ_CLEAR, TAC_CFG_BEII_IECS0_SGCP3_IB_WR_MISS_CLEAR, TAC_CFG_BEII_IECS0_SGCP4_CYC_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP4_FIFO_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP4_SEQ_CLEAR, TAC_CFG_BEII_IECS0_SGCP4_IB_WR_MISS_CLEAR, TAC_CFG_BEII_IECS0_SGCP5_CYC_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP5_FIFO_OVER_CLEAR, TAC_CFG_BEII_IECS0_SGCP5_SEQ_CLEAR, TAC_CFG_BEII_IECS0_SGCP5_IB_WR_MISS_CLEAR, TAC_CFG_BEII_IECS1_FE0_TRANS_CLEAR, TAC_CFG_BEII_IECS1_FE1_TRANS_CLEAR, TAC_CFG_BEII_IECS1_FE2_TRANS_CLEAR, TAC_CFG_BEII_IECS1_BE_WD_CLEAR

Affects
TAC_CFG_BEII_IE0_SGCP0_CYC_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP0_FIFO_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP0_SEQ_ENA=0, TAC_CFG_BEII_IE0_SGCP0_IB_WR_MISS_ENA=0, TAC_CFG_BEII_IE0_SGCP1_CYC_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP1_FIFO_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP1_SEQ_ENA=0, TAC_CFG_BEII_IE0_SGCP1_IB_WR_MISS_ENA=0, TAC_CFG_BEII_IE0_SGCP2_CYC_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP2_FIFO_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP2_SEQ_ENA=0, TAC_CFG_BEII_IE0_SGCP2_IB_WR_MISS_ENA=0, TAC_CFG_BEII_IE0_SGCP3_CYC_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP3_FIFO_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP3_SEQ_ENA=0, TAC_CFG_BEII_IE0_SGCP3_IB_WR_MISS_ENA=0, TAC_CFG_BEII_IE0_SGCP4_CYC_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP4_FIFO_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP4_SEQ_ENA=0, TAC_CFG_BEII_IE0_SGCP4_IB_WR_MISS_ENA=0, TAC_CFG_BEII_IE0_SGCP5_CYC_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP5_FIFO_OVER_ENA=0, TAC_CFG_BEII_IE0_SGCP5_SEQ_ENA=0, TAC_CFG_BEII_IE0_SGCP5_IB_WR_MISS_ENA=0, TAC_CFG_BEII_IE1_FE0_TRANS_ENA=0, TAC_CFG_BEII_IE1_FE1_TRANS_ENA=0, TAC_CFG_BEII_IE1_FE2_TRANS_ENA=0, TAC_CFG_BEII_IE1_BE_WD_ENA=0

Example

    CSL_TAC_BEII_interruptStatus  interruptsToDisable;

    // Disable the SGCP 0 FIFO Overflow interrupt
    interruptsToDisable.sgcp0FifoOverStat = 1;

    // Disable the BETI Watch Dog interrupt
    interruptsToDisable.betiWdStat        = 1;

    // Don't touch the rest of the interrupts
    interruptsToDisable.sgcp0CycOverStat  = 0;
    interruptsToDisable.sgcp0SeqStat      = 0;
    interruptsToDisable.sgcp0BuffMissStat = 0;
    interruptsToDisable.sgcp1CycOverStat  = 0;
    interruptsToDisable.sgcp1FifoOverStat = 0;
    interruptsToDisable.sgcp1BuffMissStat = 0;
    interruptsToDisable.sgcp1SeqStat      = 0;
    interruptsToDisable.sgcp2CycOverStat  = 0;
    interruptsToDisable.sgcp2FifoOverStat = 0;
    interruptsToDisable.sgcp2BuffMissStat = 0;
    interruptsToDisable.sgcp2SeqStat      = 0;
    interruptsToDisable.sgcp3CycOverStat  = 0;
    interruptsToDisable.sgcp3FifoOverStat = 0;
    interruptsToDisable.sgcp3BuffMissStat = 0;
    interruptsToDisable.sgcp3SeqStat      = 0;
    interruptsToDisable.sgcp4CycOverStat  = 0;
    interruptsToDisable.sgcp4FifoOverStat = 0;
    interruptsToDisable.sgcp4BuffMissStat = 0;
    interruptsToDisable.sgcp4SeqStat      = 0;
    interruptsToDisable.sgcp5CycOverStat  = 0;
    interruptsToDisable.sgcp5FifoOverStat = 0;
    interruptsToDisable.sgcp5BuffMissStat = 0;
    interruptsToDisable.sgcp5SeqStat      = 0;
    interruptsToDisable.fe0TransErrStat   = 0;
    interruptsToDisable.fe1TransErrStat   = 0;
    interruptsToDisable.fe2TransErrStat   = 0;

    CSL_TAC_BEII_disableInterrupts(&interruptsToDisable);
    


CSL_TAC_BEII_disableInterrupts

Description
This function disables the BEII Interrupts

Arguments

    interruptsToEnable Structure with the BETI interrupts to disable. A given
                       interrupt will be disabled if the corresponding flag is
                       set to 1.
    

Return Value
None

Pre Condition
None

Post Condition
The interrupts specified in the interruptsToDisable structure are disabled.

Writes
TAC_CFG_BEII_IECS_0_SGCP0_CYC_OVER_CLEAR, TAC_CFG_BEII_IECS_0_SGCP0_FIFO_OVER_CLEAR, TAC_CFG_BEII_IECS_0_SGCP0_SEQ_CLEAR, TAC_CFG_BEII_IECS_0_SGCP0_IB_WR_MISS_CLEAR, TAC_CFG_BEII_IECS_0_SGCP1_CYC_OVER_CLEAR, TAC_CFG_BEII_IECS_0_SGCP1_FIFO_OVER_CLEAR, TAC_CFG_BEII_IECS_0_SGCP1_SEQ_CLEAR, TAC_CFG_BEII_IECS_0_SGCP1_IB_WR_MISS_CLEAR, TAC_CFG_BEII_IECS_1_FE0_TRANS_CLEAR, TAC_CFG_BEII_IECS_1_BE_WD_CLEAR

Affects
TAC_CFG_BEII_IE_0_SGCP0_CYC_OVER_ENA=0, TAC_CFG_BEII_IE_0_SGCP0_FIFO_OVER_ENA=0, TAC_CFG_BEII_IE_0_SGCP0_SEQ_ENA=0, TAC_CFG_BEII_IE_0_SGCP0_IB_WR_MISS_ENA=0, TAC_CFG_BEII_IE_0_SGCP1_CYC_OVER_ENA=0, TAC_CFG_BEII_IE_0_SGCP1_FIFO_OVER_ENA=0, TAC_CFG_BEII_IE_0_SGCP1_SEQ_ENA=0, TAC_CFG_BEII_IE_0_SGCP1_IB_WR_MISS_ENA=0, TAC_CFG_BEII_IE_1_FE0_TRANS_ENA=0, TAC_CFG_BEII_IE_1_BE_WD_ENA=0

Example

    CSL_TAC_BEII_interruptStatus  interruptsToDisable;

    // Disable the SGCP 0 FIFO Overflow interrupt
    interruptsToDisable.sgcp0FifoOverStat = 1;

    // Disable the BETI Watch Dog interrupt
    interruptsToDisable.betiWdStat        = 1;

    // Don't touch the rest of the interrupts
    interruptsToDisable.sgcp0CycOverStat  = 0;
    interruptsToDisable.sgcp0SeqStat      = 0;
    interruptsToDisable.sgcp0BuffMissStat = 0;
    interruptsToDisable.sgcp1CycOverStat  = 0;
    interruptsToDisable.sgcp1FifoOverStat = 0;
    interruptsToDisable.sgcp1BuffMissStat = 0;
    interruptsToDisable.sgcp1SeqStat      = 0;
    interruptsToDisable.fe0TransErrStat   = 0;

    CSL_TAC_BEII_disableInterrupts(&interruptsToDisable);
    


CSL_TAC_BEII_enable

Description
This function enables the TAC2 Back End Interrupt Interface (BEII).

Arguments

    None
    

Return Value
None

Pre Condition
None

Post Condition
The Back End Interrupt Interface is enabled.

Writes
TAC_CFG_BEII_CTRL_ENABLE=1

Example

    CSL_TAC_BEII_enable();
    
void CSL_TAC_BEII_enableInterrupts ( CSL_TAC_BEII_interruptStatus *  interruptsToEnable)


CSL_TAC_BEII_enableInterrupts

Description
This function enables the BEII Interrupts

Arguments

    interruptsToEnable Structure with the BETI interrupts to enable. A given
                       interrupt will be enabled if the corresponding flag is
                       set to 1.
    

Return Value
None

Pre Condition
None

Post Condition
The interrupts specified in the interruptsToEnable structure are enabled.

Writes
TAC_CFG_BEII_IE0_SGCP0_CYC_OVER_ENA, TAC_CFG_BEII_IE0_SGCP0_FIFO_OVER_ENA, TAC_CFG_BEII_IE0_SGCP0_SEQ_ENA, TAC_CFG_BEII_IE0_SGCP0_IB_WR_MISS_ENA, TAC_CFG_BEII_IE0_SGCP1_CYC_OVER_ENA, TAC_CFG_BEII_IE0_SGCP1_FIFO_OVER_ENA, TAC_CFG_BEII_IE0_SGCP1_SEQ_ENA, TAC_CFG_BEII_IE0_SGCP1_IB_WR_MISS_ENA, TAC_CFG_BEII_IE0_SGCP2_CYC_OVER_ENA, TAC_CFG_BEII_IE0_SGCP2_FIFO_OVER_ENA, TAC_CFG_BEII_IE0_SGCP2_SEQ_ENA, TAC_CFG_BEII_IE0_SGCP2_IB_WR_MISS_ENA, TAC_CFG_BEII_IE0_SGCP3_CYC_OVER_ENA, TAC_CFG_BEII_IE0_SGCP3_FIFO_OVER_ENA, TAC_CFG_BEII_IE0_SGCP3_SEQ_ENA, TAC_CFG_BEII_IE0_SGCP3_IB_WR_MISS_ENA, TAC_CFG_BEII_IE0_SGCP4_CYC_OVER_ENA, TAC_CFG_BEII_IE0_SGCP4_FIFO_OVER_ENA, TAC_CFG_BEII_IE0_SGCP4_SEQ_ENA, TAC_CFG_BEII_IE0_SGCP4_IB_WR_MISS_ENA, TAC_CFG_BEII_IE0_SGCP5_CYC_OVER_ENA, TAC_CFG_BEII_IE0_SGCP5_FIFO_OVER_ENA, TAC_CFG_BEII_IE0_SGCP5_SEQ_ENA, TAC_CFG_BEII_IE0_SGCP5_IB_WR_MISS_ENA, TAC_CFG_BEII_IE1_FE0_TRANS_ENA, TAC_CFG_BEII_IE1_FE1_TRANS_ENA, TAC_CFG_BEII_IE1_FE2_TRANS_ENA, TAC_CFG_BEII_IE1_BE_WD_ENA

Example

    CSL_TAC_BEII_interruptStatus  interruptsToEnable;

    // Enable the SGCP 0 FIFO Overflow interrupt
    interruptsToEnable.sgcp0FifoOverStat = 1;

    // Enable the BETI Watch Dog interrupt
    interruptsToEnable.betiWdStat        = 1;

    // Don't Enable the rest of the interrupts
    interruptsToEnable.sgcp0CycOverStat  = 0;
    interruptsToEnable.sgcp0SeqStat      = 0;
    interruptsToEnable.sgcp0BuffMissStat = 0;
    interruptsToEnable.sgcp1CycOverStat  = 0;
    interruptsToEnable.sgcp1FifoOverStat = 0;
    interruptsToEnable.sgcp1BuffMissStat = 0;
    interruptsToEnable.sgcp1SeqStat      = 0;
    interruptsToEnable.sgcp2CycOverStat  = 0;
    interruptsToEnable.sgcp2FifoOverStat = 0;
    interruptsToEnable.sgcp2BuffMissStat = 0;
    interruptsToEnable.sgcp2SeqStat      = 0;
    interruptsToEnable.sgcp3CycOverStat  = 0;
    interruptsToEnable.sgcp3FifoOverStat = 0;
    interruptsToEnable.sgcp3BuffMissStat = 0;
    interruptsToEnable.sgcp3SeqStat      = 0;
    interruptsToEnable.sgcp4CycOverStat  = 0;
    interruptsToEnable.sgcp4FifoOverStat = 0;
    interruptsToEnable.sgcp4BuffMissStat = 0;
    interruptsToEnable.sgcp4SeqStat      = 0;
    interruptsToEnable.sgcp5CycOverStat  = 0;
    interruptsToEnable.sgcp5FifoOverStat = 0;
    interruptsToEnable.sgcp5BuffMissStat = 0;
    interruptsToEnable.sgcp5SeqStat      = 0;
    interruptsToEnable.fe0TransErrStat   = 0;
    interruptsToEnable.fe1TransErrStat   = 0;
    interruptsToEnable.fe2TransErrStat   = 0;

    CSL_TAC_BEII_enableInterrupts(&interruptsToEnable);
    


CSL_TAC_BEII_enableInterrupts

Description
This function enables the BEII Interrupts

Arguments

    interruptsToEnable Structure with the BETI interrupts to enable. A given
                       interrupt will be enabled if the corresponding flag is
                       set to 1.
    

Return Value
None

Pre Condition
None

Post Condition
The interrupts specified in the interruptsToEnable structure are enabled.

Writes
TAC_CFG_BEII_IE_0_SGCP0_CYC_OVER_ENA, TAC_CFG_BEII_IE_0_SGCP0_FIFO_OVER_ENA, TAC_CFG_BEII_IE_0_SGCP0_SEQ_ENA, TAC_CFG_BEII_IE_0_SGCP0_IB_WR_MISS_ENA, TAC_CFG_BEII_IE_0_SGCP1_CYC_OVER_ENA, TAC_CFG_BEII_IE_0_SGCP1_FIFO_OVER_ENA, TAC_CFG_BEII_IE_0_SGCP1_SEQ_ENA, TAC_CFG_BEII_IE_0_SGCP1_IB_WR_MISS_ENA, TAC_CFG_BEII_IE_1_FE0_TRANS_ENA, TAC_CFG_BEII_IE_1_BE_WD_ENA

Example

    CSL_TAC_BEII_interruptStatus  interruptsToEnable;

    // Enable the SGCP 0 FIFO Overflow interrupt
    interruptsToEnable.sgcp0FifoOverStat = 1;

    // Enable the BETI Watch Dog interrupt
    interruptsToEnable.betiWdStat        = 1;

    // Don't Enable the rest of the interrupts
    interruptsToEnable.sgcp0CycOverStat  = 0;
    interruptsToEnable.sgcp0SeqStat      = 0;
    interruptsToEnable.sgcp0BuffMissStat = 0;
    interruptsToEnable.sgcp1CycOverStat  = 0;
    interruptsToEnable.sgcp1FifoOverStat = 0;
    interruptsToEnable.sgcp1BuffMissStat = 0;
    interruptsToEnable.sgcp1SeqStat      = 0;
    interruptsToEnable.fe0TransErrStat   = 0;

    CSL_TAC_BEII_enableInterrupts(&interruptsToEnable);
    
void CSL_TAC_BEII_forceInterrupts ( CSL_TAC_BEII_interruptStatus *  interruptsToForce)


CSL_TAC_BEII_forceInterrupts

Description
This function sets the BEII Interrupts

Arguments

    interruptsToForce Structure with the BETI interrupts to set. A given
                      interrupt will be set if the corresponding flag is
                      set to 1.
    

Return Value
None

Pre Condition
None

Post Condition
The interrupts specified in the interruptsToForce structure are set.

Writes
TAC_CFG_BEII_IRS0_SGCP0_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP0_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP0_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP0_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS0_SGCP1_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP1_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP1_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP1_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS0_SGCP2_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP2_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP2_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP2_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS0_SGCP3_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP3_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP3_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP3_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS0_SGCP4_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP4_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP4_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP4_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS0_SGCP5_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP5_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP5_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP5_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS1_FE0_TRANS_STAT, TAC_CFG_BEII_IRS1_FE1_TRANS_STAT, TAC_CFG_BEII_IRS1_FE2_TRANS_STAT, TAC_CFG_BEII_IRS1_BE_WD_STAT

Example

    CSL_TAC_BEII_interruptStatus  interruptsToForce;

    // Force the SGCP 0 Cycle Overflow interrupt
    interruptsToForce.sgcp0CycOverStat = 1;

    // Force the SGCP 1 Input Buffer Miss Interrupt
    interruptsToForce.sgcp1BuffMissStat = 1;

    // Don't force the rest of the interrupts
    interruptsToForce.sgcp0FifoOverStat = 0;
    interruptsToForce.sgcp0SeqStat      = 0;
    interruptsToForce.sgcp0BuffMissStat = 0;
    interruptsToForce.sgcp1CycOverStat  = 0;
    interruptsToForce.sgcp1FifoOverStat = 0;
    interruptsToForce.sgcp1SeqStat      = 0;
    interruptsToForce.sgcp2CycOverStat  = 0;
    interruptsToForce.sgcp2FifoOverStat = 0;
    interruptsToForce.sgcp2SeqStat      = 0;
    interruptsToForce.sgcp2BuffMissStat = 0;
    interruptsToForce.sgcp3CycOverStat  = 0;
    interruptsToForce.sgcp3FifoOverStat = 0;
    interruptsToForce.sgcp3SeqStat      = 0;
    interruptsToForce.sgcp3BuffMissStat = 0;
    interruptsToForce.fe1TransErrStat   = 0;
    interruptsToForce.fe1TransErrStat   = 0;
    interruptsToForce.betiWdStat        = 0;

    CSL_TAC_BEII_forceInterrupts(&interruptsToForce);
    


CSL_TAC_BEII_forceInterrupts

Description
This function sets the BEII Interrupts

Arguments

    interruptsToForce Structure with the BETI interrupts to set. A given
                      interrupt will be set if the corresponding flag is
                      set to 1.
    

Return Value
None

Pre Condition
None

Post Condition
The interrupts specified in the interruptsToForce structure are set.

Writes
TAC_CFG_BEII_IRS_0_SGCP0_CYC_OVER_STAT, TAC_CFG_BEII_IRS_0_SGCP0_FIFO_OVER_STAT, TAC_CFG_BEII_IRS_0_SGCP0_SEQ_STAT, TAC_CFG_BEII_IRS_0_SGCP0_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS_0_SGCP1_CYC_OVER_STAT, TAC_CFG_BEII_IRS_0_SGCP1_FIFO_OVER_STAT, TAC_CFG_BEII_IRS_0_SGCP1_SEQ_STAT, TAC_CFG_BEII_IRS_0_SGCP1_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS_1_FE0_TRANS_STAT, TAC_CFG_BEII_IRS_1_BE_WD_STAT

Example

    CSL_TAC_BEII_interruptStatus  interruptsToForce;

    // Force the SGCP 0 Cycle Overflow interrupt
    interruptsToForce.sgcp0CycOverStat = 1;

    // Force the SGCP 1 Input Buffer Miss Interrupt
    interruptsToForce.sgcp1BuffMissStat = 1;

    // Don't force the rest of the interrupts
    interruptsToForce.sgcp0FifoOverStat = 0;
    interruptsToForce.sgcp0SeqStat      = 0;
    interruptsToForce.sgcp0BuffMissStat = 0;
    interruptsToForce.sgcp1CycOverStat  = 0;
    interruptsToForce.sgcp1FifoOverStat = 0;
    interruptsToForce.sgcp1SeqStat      = 0;
    interruptsToForce.betiWdStat        = 0;

    CSL_TAC_BEII_forceInterrupts(&interruptsToForce);
    
void CSL_TAC_BEII_getEnabledInterruptStatus ( CSL_TAC_BEII_interruptStatus *  interruptEnStatus)


CSL_TAC_BEII_getEnabledInterruptStatus

Description
This function reads the BEII Interrupt Enable Status

Arguments

    interruptEnStatus Structure with the BETI interrupt Enable status.
    

Return Value
None

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BEII_IES0_SGCP0_CYC_OVER_STAT, TAC_CFG_BEII_IES0_SGCP0_FIFO_OVER_STAT, TAC_CFG_BEII_IES0_SGCP0_SEQ_STAT, TAC_CFG_BEII_IES0_SGCP0_IB_WR_MISS_STAT, TAC_CFG_BEII_IES0_SGCP1_CYC_OVER_STAT, TAC_CFG_BEII_IES0_SGCP1_FIFO_OVER_STAT, TAC_CFG_BEII_IES0_SGCP1_SEQ_STAT, TAC_CFG_BEII_IES0_SGCP1_IB_WR_MISS_STAT, TAC_CFG_BEII_IES0_SGCP2_CYC_OVER_STAT, TAC_CFG_BEII_IES0_SGCP2_FIFO_OVER_STAT, TAC_CFG_BEII_IES0_SGCP2_SEQ_STAT, TAC_CFG_BEII_IES0_SGCP2_IB_WR_MISS_STAT, TAC_CFG_BEII_IES0_SGCP3_CYC_OVER_STAT, TAC_CFG_BEII_IES0_SGCP3_FIFO_OVER_STAT, TAC_CFG_BEII_IES0_SGCP3_SEQ_STAT, TAC_CFG_BEII_IES0_SGCP3_IB_WR_MISS_STAT, TAC_CFG_BEII_IES0_SGCP4_CYC_OVER_STAT, TAC_CFG_BEII_IES0_SGCP4_FIFO_OVER_STAT, TAC_CFG_BEII_IES0_SGCP4_SEQ_STAT, TAC_CFG_BEII_IES0_SGCP4_IB_WR_MISS_STAT, TAC_CFG_BEII_IES0_SGCP5_CYC_OVER_STAT, TAC_CFG_BEII_IES0_SGCP5_FIFO_OVER_STAT, TAC_CFG_BEII_IES0_SGCP5_SEQ_STAT, TAC_CFG_BEII_IES0_SGCP5_IB_WR_MISS_STAT, TAC_CFG_BEII_IES1_FE0_TRANS_STAT, TAC_CFG_BEII_IES1_FE1_TRANS_STAT, TAC_CFG_BEII_IES1_FE2_TRANS_STAT, TAC_CFG_BEII_IES1_BE_WD_STAT

Example

    CSL_TAC_BEII_interruptStatus  interruptEnStatus;

    CSL_TAC_BEII_getEnabledInterruptStatus(&interruptEnStatus);

    if (interruptEnStatus.sgcp0CycOverStat)
    {
        // SGCP 0 Cycle Overflow Interrupt is enabled
        ...
    }

    


CSL_TAC_BEII_getEnabledInterruptStatus

Description
This function reads the BEII Interrupt Enable Status

Arguments

    interruptEnStatus Structure with the BETI interrupt Enable status.
    

Return Value
None

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BEII_IES_0_SGCP0_CYC_OVER_STAT, TAC_CFG_BEII_IES_0_SGCP0_FIFO_OVER_STAT, TAC_CFG_BEII_IES_0_SGCP0_SEQ_STAT, TAC_CFG_BEII_IES_0_SGCP0_IB_WR_MISS_STAT, TAC_CFG_BEII_IES_0_SGCP1_CYC_OVER_STAT, TAC_CFG_BEII_IES_0_SGCP1_FIFO_OVER_STAT, TAC_CFG_BEII_IES_0_SGCP1_SEQ_STAT, TAC_CFG_BEII_IES_0_SGCP1_IB_WR_MISS_STAT, TAC_CFG_BEII_IES_1_FE0_TRANS_STAT, TAC_CFG_BEII_IES_1_BE_WD_STAT

Example

    CSL_TAC_BEII_interruptStatus  interruptEnStatus;

    CSL_TAC_BEII_getEnabledInterruptStatus(&interruptEnStatus);

    if (interruptEnStatus.sgcp0CycOverStat)
    {
        // SGCP 0 Cycle Overflow Interrupt is enabled
        ...
    }

    
CSL_TAC_BEII_enableStatus CSL_TAC_BEII_getEnableStatus ( )


CSL_TAC_BEII_getEnableStatus

Description
This function returns the enable status of the BEII.

Arguments

    None
    

Return Value
CSL_TAC_BEII_Disabled The BEII is disabled.
CSL_TAC_BEII_Enabled The BEII is enabled.

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BEII_CTRL_ENABLE

Example

    CSL_TAC_BEII_enable();

    if (CSL_TAC_BEII_getEnableStatus() != CSL_TAC_BEII_Enabled)
    {
        // The BEII should have been enabled.
        ...
    }

    ...
    CSL_TAC_BEII_disable();

    if (CSL_TAC_BEII_getEnableStatus() != CSL_TAC_BEII_Disabled)
    {
        // The BEII should have been disabled.
        ...
    }
    
Uint32 CSL_TAC_BEII_getEOI ( )


CSL_TAC_BEII_getEOI

Description
This function returns the contents of BEII End of Interrupt register.

Arguments

    None
    

Return Value
Uint32

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BEII_EOI_EOI

Example

    Uint32  eoiVal;

    eoiVal = CSL_TAC_BEII_getEOI();
    
void CSL_TAC_BEII_getInterruptStatus ( CSL_TAC_BEII_interruptStatus *  interruptStatus)


CSL_TAC_BEII_getInterruptStatus

Description
This function reads the BEII Interrupt Status

Arguments

    interruptStatus Structure with the active BETI interrupt status.
    

Return Value
None

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BEII_IRS0_SGCP0_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP0_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP0_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP0_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS0_SGCP1_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP1_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP1_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP1_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS0_SGCP2_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP2_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP2_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP2_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS0_SGCP3_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP3_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP3_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP3_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS0_SGCP4_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP4_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP4_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP4_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS0_SGCP5_CYC_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP5_FIFO_OVER_STAT, TAC_CFG_BEII_IRS0_SGCP5_SEQ_STAT, TAC_CFG_BEII_IRS0_SGCP5_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS1_FE0_TRANS_STAT, TAC_CFG_BEII_IRS1_FE1_TRANS_STAT, TAC_CFG_BEII_IRS1_FE2_TRANS_STAT, TAC_CFG_BEII_IRS1_BE_WD_STAT

Example

    CSL_TAC_BEII_interruptStatus  interruptStatus;

    CSL_TAC_BEII_getInterruptStatus(&interruptStatus);

    if (interruptStatus.sgcp0CycOverStat)
    {
        // SGCP 0 Cycle Overflow Interrupt occured
        ...
    }

    if (interruptStatus.sgcp0FifoOverStat)
    {
        // SGCP 0 FIFO Overflow Interrupt occured
        ...
    }

    if (interruptStatus.sgcp0SeqStat)
    {
        // SGCP 0 Cycle Sequencer Idle Interrupt occured
        ...
    }

    if (interruptStatus.sgcp0BuffMissStat)
    {
        // SGCP 0 Input Buffer Miss Interrupt occured
        ...
    }

    if (interruptStatus.sgcp1CycOverStat)
    {
        // SGCP 1 Cycle Overflow Interrupt occured
        ...
    }

    if (interruptStatus.sgcp1FifoOverStat)
    {
        // SGCP 1 FIFO Overflow Interrupt occured
        ...
    }

    if (interruptStatus.sgcp1SeqStat)
    {
        // SGCP 1 Cycle Sequencer Idle Interrupt occured
        ...
    }

    if (interruptStatus.sgcp1BuffMissStat)
    {
        // SGCP 1 Input Buffer Miss Interrupt occured
        ...
    }

    ...
    // Checks for SGCP 2,3,4,5, if necesssary
    ...

    if (interruptStatus.fe0TransErrStat)
    {
        // Front-End # 0 Transaction ID unavailable
        ...
    }

    if (interruptStatus.fe1TransErrStat)
    {
        // Front-End #1 Transaction ID unavailable
        ...
    }

    if (interruptStatus.fe2TransErrStat)
    {
        // Front-End #2 Transaction ID unavailable
        ...
    }

    if (interruptStatus.betiWdStat)
    {
        // The Back-End Watch Dog Timer counter reached 0
        ...
    }

    


CSL_TAC_BEII_getInterruptStatus

Description
This function reads the BEII Interrupt Status

Arguments

    interruptStatus Structure with the active BETI interrupt status.
    

Return Value
None

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BEII_IRS_0_SGCP0_CYC_OVER_STAT, TAC_CFG_BEII_IRS_0_SGCP0_FIFO_OVER_STAT, TAC_CFG_BEII_IRS_0_SGCP0_SEQ_STAT, TAC_CFG_BEII_IRS_0_SGCP0_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS_0_SGCP1_CYC_OVER_STAT, TAC_CFG_BEII_IRS_0_SGCP1_FIFO_OVER_STAT, TAC_CFG_BEII_IRS_0_SGCP1_SEQ_STAT, TAC_CFG_BEII_IRS_0_SGCP1_IB_WR_MISS_STAT, TAC_CFG_BEII_IRS_1_FE0_TRANS_STAT, TAC_CFG_BEII_IRS_1_BE_WD_STAT

Example

    CSL_TAC_BEII_interruptStatus  interruptStatus;

    CSL_TAC_BEII_getInterruptStatus(&interruptStatus);

    if (interruptStatus.sgcp0CycOverStat)
    {
        // SGCP 0 Cycle Overflow Interrupt occured
        ...
    }

    if (interruptStatus.sgcp0FifoOverStat)
    {
        // SGCP 0 FIFO Overflow Interrupt occured
        ...
    }

    if (interruptStatus.sgcp0SeqStat)
    {
        // SGCP 0 Cycle Sequencer Idle Interrupt occured
        ...
    }

    if (interruptStatus.sgcp0BuffMissStat)
    {
        // SGCP 0 Input Buffer Miss Interrupt occured
        ...
    }

    if (interruptStatus.sgcp1CycOverStat)
    {
        // SGCP 1 Cycle Overflow Interrupt occured
        ...
    }

    if (interruptStatus.sgcp1FifoOverStat)
    {
        // SGCP 1 FIFO Overflow Interrupt occured
        ...
    }

    if (interruptStatus.sgcp1SeqStat)
    {
        // SGCP 1 Cycle Sequencer Idle Interrupt occured
        ...
    }

    if (interruptStatus.sgcp1BuffMissStat)
    {
        // SGCP 1 Input Buffer Miss Interrupt occured
        ...
    }

    if (interruptStatus.fe0TransErrStat)
    {
        // Front-End # 0 Transaction ID unavailable
        ...
    }

    if (interruptStatus.betiWdStat)
    {
        // The Back-End Watch Dog Timer counter reached 0
        ...
    }

    
void CSL_TAC_BEII_setEOI ( Uint32  eoiVecValue)


CSL_TAC_BEII_setEOI

Description
This function configures the BEII End of Interrupt register.

Arguments

    eoiVecValue       EOI Vector value
    None
    

Return Value
None

Pre Condition
None

Post Condition
None

Writes
TAC_CFG_BEII_EOI_EOI

Example

    CSL_TAC_BEII_setEOI(5000);
    


CSL_TAC_BETI_clearWatchDogInterrupt

Description
This function clears the interrupt registered in the watch dog interrupt status register.

Arguments

    None
    

Return Value
None

Pre Condition
None

Post Condition
None

Writes
TAC_CFG_BETI_WINT_INT_STAT=0

Example

    CSL_TAC_BETI_wdInterruptStatus wdIntStatus;

    wdIntStatus = CSL_TAC_BETI_getWatchDogInterruptStatus();

    if (wdIntStatus == CSL_TAC_BETI_wdInterruptStatus_Int)
    {
        // Interrupt generated and forwarded to BEII
        CSL_TAC_BETI_clearWatchDogInterrupt();
    }
    


CSL_TAC_BETI_disable

Description
This function disables the TAC2 Back End Transfer Interface (BETI).

Arguments

    None
    

Return Value
None

Pre Condition
None

Post Condition
The Back End Transfer Interface is disabled.

Writes
TAC_CFG_BETI_CTRL_ENABLE=0

Example

    CSL_TAC_BETI_disable();
    


CSL_TAC_BETI_enable

Description
This function enables the TAC2 Back End Transfer Interface (BETI).

Arguments

    None
    

Return Value
None

Pre Condition
None

Post Condition
The Back End Transfer Interface is enabled.

Writes
TAC_CFG_BETI_CTRL_ENABLE=1

Example

    CSL_TAC_BETI_enable();
    
CSL_TAC_BETI_enableStatus CSL_TAC_BETI_getEnableStatus ( )


CSL_TAC_BETI_getEnableStatus

Description
This function returns the enable status of the BETI.

Arguments

    None
    

Return Value
CSL_TAC_BETI_Disabled The BETI is disabled.
CSL_TAC_BETI_Enabled The BETI is enabled.

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BETI_CTRL_ENABLE

Example

    CSL_TAC_BETI_enable();

    if (CSL_TAC_BETI_getEnableStatus() != CSL_TAC_BETI_Enabled)
    {
        // The BETI should have been enabled.
        ...
    }

    ...
    CSL_TAC_BETI_disable();

    if (CSL_TAC_BETI_getEnableStatus() != CSL_TAC_BETI_Disabled)
    {
        // The BETI should have been disabled.
        ...
    }
    
void CSL_TAC_BETI_getStatus ( CSL_TAC_BETI_status *  betiStatus)


CSL_TAC_BETI_getStatus

Description
This function returns the BETI status indicating whether the SGCPs are Busy or Idle.

Arguments

    betiStatus     Status of the SGCPs
    

Return Value None

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BETI_STAT_SGCP0_STATUS, TAC_CFG_BETI_STAT_SGCP1_STATUS

Example

    CSL_TAC_BETI_status  betiStatus;

    CSL_TAC_BETI_getStatus(&betiStatus);

    if (betiStatus.sgcp0Status == CSL_TAC_BETI_statusBit_Idle)
    {
        // SGCP 0 Idle
        ...
    }

    if (betiStatus.sgcp1Status == CSL_TAC_BETI_statusBit_Busy)
    {
        // SGCP 1 Busy
        ...
    }

    if (betiStatus.sgcp2Status == CSL_TAC_BETI_statusBit_Busy)
    {
        // SGCP 2 Busy
        ...
    }

    if (betiStatus.sgcp3Status == CSL_TAC_BETI_statusBit_Idle)
    {
        // SGCP 3 Idle
        ...
    }


    


CSL_TAC_BETI_getStatus

Description
This function returns the BETI status indicating whether the SGCPs are Busy or Idle.

Arguments

    betiStatus     Status of the SGCPs
    

Return Value None

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BETI_STAT_SGCP0_STATUS, TAC_CFG_BETI_STAT_SGCP1_STATUS

Example

    CSL_TAC_BETI_status  betiStatus;

    CSL_TAC_BETI_getStatus(&betiStatus);

    if (betiStatus.sgcp0Status == CSL_TAC_BETI_statusBit_Idle)
    {
        // SGCP 0 Idle
        ...
    }

    if (betiStatus.sgcp1Status == CSL_TAC_BETI_statusBit_Busy)
    {
        // SGCP 1 Busy
        ...
    }


    
CSL_TAC_BETI_wdInterruptStatus CSL_TAC_BETI_getWatchDogInterruptStatus ( )


CSL_TAC_BETI_getWatchDogInterruptStatus

Description
This function reads the content of the watch dog interrupt status register.

Arguments

    None
    

Return Value
CSL_TAC_BETI_wdInterruptStatus_NoInt No interrupt has been generated.
CSL_TAC_BETI_wdInterruptStatus_Int An interrupt has been generated and forwarded to the BEII.

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BETI_WINT_INT_STAT

Example

    CSL_TAC_BETI_wdInterruptStatus wdIntStatus;

    wdIntStatus = CSL_TAC_BETI_getWatchDogInterruptStatus();

    if (wdIntStatus == CSL_TAC_BETI_wdInterruptStatus_Int)
    {
        // Interrupt generated and forwarded to BEII
        ...
    }
    


CSL_TAC_BETI_getWatchDogStatus

Description
This function reads the content of the BETI watch dog decounter.

Arguments

    None
    

Return Value
Current value of the decounter.

Pre Condition
None

Post Condition
None

Reads
TAC_CFG_BETI_WST_BE_WD_STAT

Example

    Uint16  deCnt;

    deCnt = CSL_TAC_BETI_getWatchDogStatus();
    ...
    
void CSL_TAC_BETI_setWatchDog ( Uint16  reloadCnt)


CSL_TAC_BETI_setWatchDog

Description
This function configures the watch dog in the BETI.

Arguments

    reloadCnt       The value indicates the number of elapsed TAC2 clock cycles
                    between DMA write accesses that will trigger a watchdog
                    interrupt.
    

Return Value None

Pre Condition
None

Post Condition
The Back-End watch-dog is configured.

Writes
TAC_CFG_BETI_WCFG_BE_WD_CFG

Example

    CSL_TAC_BETI_setWatchDog(100);
    

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