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Specification of the SerDes Control And Status 1 Register. More...
#include <hyplnk.h>
Data Fields | |
uint32_t | raw |
[ro] Raw image of register on read; actual value on write | |
uint8_t | sleepCnt |
[rw] Sleep mask count | |
uint8_t | disableCnt |
[rw] Disable mask count |
Specification of the SerDes Control And Status 1 Register.
The SerDes Control and Status 1 Register is used to define the mask time that the receive lane data is ignored after enabling the lane(s) from either a sleep or disabled state. The default numbers of these counters are not yet determined. When these counters are zero, there are no delays in link establishment. This register delays the start of link establishment or step up link by a number of symbol times sixteen.
[rw] Disable mask count
Field size: 8 bits
This count times 16 SerDes symbol times are masked for SerDes lanes that enter a disabled state. This allows the SerDes CDR and equalizer to stabilize before the link is established
[rw] Sleep mask count
Field size: 8 bits
This count times 16 SerDes symbol times are masked for SerDes lanes that enter a sleep/enable state. This allows the internal SerDes power supplies to stabilize before the link is established.