Qmss_LinkingRAM Struct Reference
[QMSS Low Level Driver Data Structures]

QMSS configuration structure. More...

#include <qmss_qm.h>


Data Fields

uint32_t linkingRAM0Base
uint32_t linkingRAM0Size
uint32_t linkingRAM1Base
uint32_t maxDescNum


Detailed Description

QMSS configuration structure.


Field Documentation

uint32_t Qmss_LinkingRAM::linkingRAM0Base

Base address of Linking RAM 0. LLD will configure linking RAM0 address to internal linking RAM address if a value of zero is specified.

uint32_t Qmss_LinkingRAM::linkingRAM0Size

Linking RAM 0 Size. LLD will configure linking RAM0 size to maximum internal linking RAM size if a value of zero is specified

uint32_t Qmss_LinkingRAM::linkingRAM1Base

Base address of Linking RAM 1. Depends on RAM 0 Size and total number of descriptors. If linkingRAM1Base is zero then linkingRAM0Size must be large enough to store all descriptors in the system

uint32_t Qmss_LinkingRAM::maxDescNum

Maximum number of descriptors in the system. Should be equal to less than the RAM0+RAM1 size


The documentation for this struct was generated from the following file:
Copyright 2014, Texas Instruments Incorporated