Data Fields
pcieSymTimerFltMaskReg_s Struct Reference

Specification of the Symbol Timer and Filter Mask register. More...

#include <pcie.h>

Data Fields

uint32_t raw
uint8_t f1CfgDrop
 [rw] 1 = Allow CFG transaction being received on RC.
uint8_t f1IoDrop
 [rw] 1 = Allow IO transaction being received on RC.
uint8_t f1MsgDrop
 [rw] 1 = Allow MSG transaction being received on RC.
uint8_t f1CplEcrcDrop
 [rw] 1 = Allow completion TLPs with ECRC errors to be passed up.
uint8_t f1EcrcDrop
 [rw] 1 = Allow TLPs with ECRC errors to be passed up.
uint8_t f1CplLenTest
 [rw] 1 = Mask length match for received completion TLPs.
uint8_t f1CplAttrTest
 [rw] 1 = Mask attribute match on received completion TLPs.
uint8_t f1CplTcTest
 [rw] 1 = Mask traffic class match on received completion TLPs.
uint8_t f1CplFuncTest
 [rw] 1 = Mask function match for received completion TLPs.
uint8_t f1CplReqIDTest
 [rw] 1 = Mask request ID match for received completion TLPs.
uint8_t f1CplTagErrTest
 [rw] 1 = Mask tag error rules for received completion TLPs.
uint8_t f1LockedRdAsUr
 [rw] 1 = Treat locked read TLPs as supported for EP, UR for RC.
uint8_t f1Cfg1ReAsUs
 [rw] 1 = Treat type 1 CFG TLPs as supported for EP and UR for RC.
uint8_t f1UrOutOfBar
 [rw] 1 = Treat out-of-BAR TLPs as supported requests.
uint8_t f1UrPoison
 [rw] 1 = Treat poisoned TLPs as supported requests.
uint8_t f1UrFunMismatch
 [rw] 1 = Treat function mismatched TLPs as supported requests.
uint8_t fcWdogDisable
 [rw] 1 = Disable Flow Control watchdog timer.
uint16_t skpValue
 [rw] Wait time between SKP ordered sets

Detailed Description

Specification of the Symbol Timer and Filter Mask register.

This register may be used for both endpoint and root complex modes.


Field Documentation

[rw] 1 = Treat type 1 CFG TLPs as supported for EP and UR for RC.

Field size: 1 bit

[rw] 1 = Allow CFG transaction being received on RC.

Field size: 1 bit

[rw] 1 = Mask attribute match on received completion TLPs.

Field size: 1 bit

[rw] 1 = Allow completion TLPs with ECRC errors to be passed up.

Field size: 1 bit

[rw] 1 = Mask function match for received completion TLPs.

Field size: 1 bit

[rw] 1 = Mask length match for received completion TLPs.

Field size: 1 bit

[rw] 1 = Mask request ID match for received completion TLPs.

Field size: 1 bit

[rw] 1 = Mask tag error rules for received completion TLPs.

Field size: 1 bit

[rw] 1 = Mask traffic class match on received completion TLPs.

Field size: 1 bit

[rw] 1 = Allow TLPs with ECRC errors to be passed up.

Field size: 1 bit

[rw] 1 = Allow IO transaction being received on RC.

Field size: 1 bit

[rw] 1 = Treat locked read TLPs as supported for EP, UR for RC.

Field size: 1 bit

[rw] 1 = Allow MSG transaction being received on RC.

Field size: 1 bit

[rw] 1 = Treat function mismatched TLPs as supported requests.

Field size: 1 bit

[rw] 1 = Treat out-of-BAR TLPs as supported requests.

Field size: 1 bit

[rw] 1 = Treat poisoned TLPs as supported requests.

Field size: 1 bit

[rw] 1 = Disable Flow Control watchdog timer.

Field size: 1 bit

[ro] Raw image of register on read; actual value on write

[rw] Wait time between SKP ordered sets

Number of symbol times to wait between transmitting SKP ordered sets. For example, for a setting of 1536 decimal, the wait will be for 1537 symbol times.

Field size: 11 bits


The documentation for this struct was generated from the following file:

Copyright 2014, Texas Instruments Incorporated