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Specification of the Device Status and Control Register 2. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
uint8_t | cmplToDis |
[rw] Completion timeout disable | |
uint8_t | cmplTo |
[rw] Completion timeout value. |
Specification of the Device Status and Control Register 2.
This register may be used for both endpoint and root complex modes.
uint8_t pcieDevStatCtrl2Reg_s::cmplTo |
[rw] Completion timeout value.
It is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.
cmplTo | low range | high range |
---|---|---|
0x0 | 50ms | 50s |
0x1 | 50s | 100s |
0x2 | 1ms | 10ms |
0x5 | 16ms | 55ms |
0x6 | 65ms | 210ms |
0x9 | 260ms | 900ms |
0xA | 1s | 3.5s |
0xD | 4s | 13s |
0xE | 17s | 64s |
others | reserved | reserved |
Field size: 4 bits
uint8_t pcieDevStatCtrl2Reg_s::cmplToDis |
[rw] Completion timeout disable
Field size: 1 bit
uint32_t pcieDevStatCtrl2Reg_s::raw |
[ro] Raw image of register on read; actual value on write