Packet Accelerator Low Level Driver
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Introduction

The packet accelerator sub-system (PASS) is designed to provide the input packet classification, checksum/CRC verification and generation, data manipulation and etc. The first generation PASS consists of the following resources

The packet accelerator low level driver (PA LLD) provides configuration and control of the packet accelerator sub-system (PASS). The sub-system provides from network packet classification and routing based on network header information (see netlayers). The packet accelerator low level driver module (referred to as the module) provides APIs to configure the criteria used for from-network packet routing.

The module attempts to abstract the operation of the PASS from the application. The module uses the following rules when configuring the PASS:

With the exception of some initial setup functions, the module does not communicate directly with the sub-system. The output of the module is a formatted data block along with a destination address. The module user must send the formatted data to the sub-system. This is typically done by linking the created data block to a host packet descriptor, and then using the addressing information to send the created packet to the sub-system through the queue manager and PKTDMA.

For packets to the network, the sub-system provides ones complement checksum or CRC generation over a range provided by the module user. The range is not determined by sub-system by parsing the to-network packet, since it is assumed that the creator of the packet already has the start offset, length, initial checksum value and etc.

The low level driver maintains two tables of layer 2 and layer 3 configuration information. The memory for these tables is provided by the module user at run time. The module maintains ownership of these tables and the module user must not write to the memory once provided to the module.

In multi-core devices the module can be used in two different configurations. In independent core mode each core in a device has a unique set of tables. Although it is legal for any core to reference handles from other cores, this is not typically done. In this case cache coherency and cross core semaphores are not implemented by the module user. In common core mode there is only one set of tables and they are shared by all cores. Each core that uses the module must initialize it, but each core will provide the exact same buffers to the module. The module user will have the first core to initialize the module also initialize the table. Other cores will initialize their internal state but not initialize the table. In this mode cache coherency and cross core semaphores must be implemented by the module user to insure the integrity of the tables.

The second generation of the packet accelerator sub-system (PASS) of the new Keystone2 device is enhanced to support fully-offloaded fast-path operations in both ingress and egress directions. The second generation PASS provides the following functionalities:

The second generation PASS consists of five ingress stages (Ingress0-4), a post-processing stage (Post) and three egress stages (Egress 0-2). Each stage has its intended function, which is described briefly in the sub-sections below. Ingress packets (from the Ethernet Switch through PA to the host) are expected to follow the flow Ingress 0 -> Ingress 1 -> Ingress 2 -> Ingress 3-> Ingress 4 -> Post -> Host. Egress packets (from the host through PA out the switch) are expected to follow the flow Egress 0 -> Egress 1 -> Egress 2 -> Ethernet Switch. Ingress packets can be directly routed to egress path without host intervention. The packets can also be routed between PASS and SASS (Security Accelerator sub-system) multiple times to perform encryption, decryption and authentication operation.

The second generation PASS also provides a Reassembly engine (RA) which can be connected from Ingress 0 and Ingress 3 stage to perform outer and inner IP reassembly and the reassembled packets will be delivered to Ingress 1 and Ingress 4 stage respectively. Besides, there is a programmable statistics engine which is used to provide PASS system statistics, ACL and Flow cache pre-entry statistics and user-defined statistics.

To maintain backward compatibility, the second generation PASS LLD maintains the same APIs of the first generation LLD. New APIs are added for the new features such as ACL, Flow Cache and etc only.


Copyright 2014, Texas Instruments Incorporated