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Specification of the Link Capabilities Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
uint8_t | portNum |
[rw] Port Number. Writable from internal bus interface. | |
uint8_t | bwNotifyCap |
[rw] Bandwidth Notification Capable. | |
uint8_t | dllRepCap |
[rw] Link Layer Active Reporting Capable. | |
uint8_t | downErrRepCap |
[rw] Surprise Down Error Reporting Capable. Not supported. Always zero. | |
uint8_t | clkPwrMgmt |
[rw] Clock Power Management. Writable from internal bus interface. | |
uint8_t | l1ExitLat |
[rw] L1 Exit Latency when common clock is used. Writable from internal bus interface. | |
uint8_t | losExitLat |
[rw] L0s Exit Latency. Writable from internal bus interface. | |
uint8_t | asLinkPm |
[rw] Active State Link Power Management Support. Writable from internal bus interface. | |
uint8_t | maxLinkWidth |
[rw] Maximum Link Width. Writable from internal bus interface. | |
uint8_t | maxLinkSpeed |
[rw] Maximum Link Speed. Writable from internal bus interface. |
Specification of the Link Capabilities Register.
This register may be used for both endpoint and root complex modes.
uint8_t pcieLinkCapReg_s::asLinkPm |
[rw] Active State Link Power Management Support. Writable from internal bus interface.
1h = L0s entry supported.
3h = L0s and L1 supported.
Others = Reserved.
Field size: 2 bits
uint8_t pcieLinkCapReg_s::bwNotifyCap |
[rw] Bandwidth Notification Capable.
0 = For upstream ports (EP ports)
1 = For downstream ports (RC ports)
Field size: 1 bit
uint8_t pcieLinkCapReg_s::clkPwrMgmt |
[rw] Clock Power Management. Writable from internal bus interface.
For upstream ports (EP Ports), a value of 1h in this bit indicates that the component tolerates the removal of any reference clock(s) in the L1 and L2/L3 Ready Link states. A value of 0 indicates the reference clock(s) must not be removed in these Link states.
For downstream ports (RC Ports), this bit is always 0.
Field size: 1 bit
uint8_t pcieLinkCapReg_s::dllRepCap |
[rw] Link Layer Active Reporting Capable.
0 = For upstream ports (EP ports)
1 = For downstream ports (RC ports)
Field size: 1 bit
uint8_t pcieLinkCapReg_s::downErrRepCap |
[rw] Surprise Down Error Reporting Capable. Not supported. Always zero.
Field size: 1 bit
uint8_t pcieLinkCapReg_s::l1ExitLat |
[rw] L1 Exit Latency when common clock is used. Writable from internal bus interface.
l1ExitLat | low range | high range |
---|---|---|
0 | 0 | 64 ns |
1 | 64ns | 128ns |
2 | 128ns | 256ns |
3 | 256ns | 512ns |
4 | 512ns | 1µs |
5 | 1µs | 2µs |
6 | 2µs | 4µs |
7 | 4µs | and up |
Field size: 3 bits
uint8_t pcieLinkCapReg_s::losExitLat |
[rw] L0s Exit Latency. Writable from internal bus interface.
l1ExitLat | low range | high range |
---|---|---|
0 | 0 | 64 ns |
1 | 64ns | 128ns |
2 | 128ns | 256ns |
3 | 256ns | 512ns |
4 | 512ns | 1µs |
5 | 1µs | 2µs |
6 | 2µs | 4µs |
7 | 4µs | and up |
Field size: 3 bits
uint8_t pcieLinkCapReg_s::maxLinkSpeed |
[rw] Maximum Link Speed. Writable from internal bus interface.
1h = 2.5GT/s Link speed supported.
2h = 5.0 GT/s and 2.5 GT/s Link speeds supported.
Others = Reserved.
Field size: 4 bits
uint8_t pcieLinkCapReg_s::maxLinkWidth |
[rw] Maximum Link Width. Writable from internal bus interface.
1h = ×1
2h = ×2
Others = Reserved.
Field size: 6 bits
uint8_t pcieLinkCapReg_s::portNum |
[rw] Port Number. Writable from internal bus interface.
Field size: 8 bits
uint32_t pcieLinkCapReg_s::raw |
[ro] Raw image of register on read; actual value on write