Data Fields
_Fftc_ControlRegCfg Struct Reference

Fftc_ControlRegCfg. More...

#include <fftc_lld.h>

Data Fields

uint32_t dftSize
Fftc_DFTMode dftMode
uint8_t bEmulateDSP16x16
uint8_t bZeroPadEnable
Fftc_ZeroPadMode zeroPadMode
uint32_t zeroPadFactor
uint8_t bSupressSideInfo
uint8_t bIqOrder
uint8_t bIqSize

Detailed Description

Fftc_ControlRegCfg.

Structure to specify/hold the FFTC Queue X Control Register configuration info for a given FFTC queue.


Field Documentation

Not used on FFTC, always set to zero.

Boolean flag, set to 1 to reverse I/Q order assumend on the input.

Corresponds to the 'iq_order' bit field of the FFTC Queue X Control Register.

Boolean flag, set to 1 to use 8-bit I/Q format. The order convention is followed using iq_order.

The 8-bit sample mode has some restrictions 1) Cyclic prefix removal is not supported. 2) DFT size must be a multiple of 8 samples. DFT sizes NOT supported are 4, 12, 36, 60, 108, 180, 324, 972, 540, 300, 900 3) The resulting data length from zero padding must be a multiple of 8.

Corresponds to the 'iq_size' bit field of the FFTC Queue X Control Register.

Boolean flag, set to 1 to supress FFTC side info such as block exponent, clipping detection, error and tag being output.

Corresponds to the 'supress_side_info' bit field of the FFTC Queue X Control Register.

Boolean Flag, set to 1 to enable zero padding.

DFT/IDFT selection configuration.

Mode can be either 0 for an IFFT/IDFT, 1 for FFT/DFT.

Corresponds to the 'DFT_IDFT_select' bit field of the FFTC Queue X Control Register.

DFT Block size in bytes - size of the transform

Corresponds to the 'DFT_size' bit field of the FFTC Queue X Control Register. A list of the DFT block sizes supported by the FFTC hardware is documented in the FFTC User Guide.

The number of samples to use for zero padding in "Add" mode or the multiplication factor by which the oversampling needs to be done in "Multiply" mode for zero padding. Setting this to "0" disables zero padding in both modes.

In "add" mode, this value must be a multiple of 4. In "multiply" mode, this value must be set such that the data length is a multiple of 4. Please consult the user guide for a table of legal values.

Corresponds to the 'zero_pad_val' bit field of the FFTC Queue X Control Register.

Zero Pad Mode. Mode can be either "add" or "multiply"

Corresponds to the 'zero_pad_mode' bit field of the FFTC Queue X Control Register.


The documentation for this struct was generated from the following file:

Copyright 2014, Texas Instruments Incorporated