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Functions | |
CSL_IDEF_INLINE CSL_SERDES_RESULT | CSL_PCIeSerdesInit (uint32_t base_addr, CSL_SERDES_REF_CLOCK ref_clock, CSL_SERDES_LINK_RATE rate) |
CSL_IDEF_INLINE void | CSL_PCIeSerdesLaneConfig (uint32_t base_addr, CSL_SERDES_REF_CLOCK ref_clock, CSL_SERDES_LINK_RATE rate, uint32_t lane_num) |
CSL_IDEF_INLINE void | CSL_PCIeSerdesComEnable (uint32_t base_addr) |
CSL_IDEF_INLINE void | CSL_PCIeSerdesSetLoopback (uint32_t base_addr, uint32_t lane_num, CSL_SERDES_LOOPBACK loopback_mode) |
CSL_IDEF_INLINE void | CSL_PCIeSerdesLaneEnable (uint32_t base_addr, uint32_t num_lanes) |
CSL_IDEF_INLINE void | CSL_PCIeSerdesLaneDisable (uint32_t base_addr, uint32_t lane_num) |
CSL_IDEF_INLINE void | CSL_PCIeSerdesLaneReset (uint32_t base_addr, uint32_t lane_num) |
CSL_IDEF_INLINE void | CSL_PCIeSerdesSetLaneRate (uint32_t base_addr, CSL_SERDES_PCIE_LANE_RATE lane_ctrl_rate) |
CSL_IDEF_INLINE CSL_SERDES_STATUS | CSL_PCIeSerdesGetStatus (uint32_t base_addr, uint32_t num_lanes) |
CSL_IDEF_INLINE CSL_SERDES_STATUS | CSL_PCIeSerdesGetPLLStatus (uint32_t base_addr) |
CSL_IDEF_INLINE CSL_SERDES_STATUS | CSL_PCIeSerdesGetLaneStatus (uint32_t base_addr, uint32_t lane_num) |
CSL_IDEF_INLINE CSL_SERDES_STATUS | CSL_PCIeSerdesGetMuxStatus (uint32_t base_addr, uint32_t num_lanes) |
CSL_IDEF_INLINE void | CSL_PCIeSerdesShutdown (uint32_t base_addr) |
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This module deals with setting up SERDES configuration for PCIE. The API flow should be as follows:
CSL_PCIeSerdesInit (base_addr, ref_clock, rate);
CSL_PCIeSerdesLaneConfig (base_addr, ref_clock, rate, lane_num);
CSL_PCIeSerdesComEnable (base_addr);
CSL_PCIeSerdesSetLoopback (base_addr, lane_num, loopback_mode);
CSL_PCIeSerdesLaneEnable (base_addr, num_lanes);
CSL_PCIeSerdesSetLaneRate (base_addr, lane_ctrl_rate);
CSL_PCIeSerdesGetStatus (base_addr, num_lanes);
OR
CSL_PCIeSerdesGetPLLStatus (base_addr);
CSL_PCIeSerdesGetLaneStatus (base_addr, lane_num); (For individual lane status)
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CSL_IDEF_INLINE void CSL_PCIeSerdesComEnable | ( | uint32_t | base_addr | ) |
============================================================================
CSL_PCIeSerdesComEnable
Description
This API enables the Serdes CMU and COMLANE
Arguments base_addr
Return Value None
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesComEnable(CSL_PCIE_SERDES_CFG_REGS);
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CSL_IDEF_INLINE CSL_SERDES_STATUS CSL_PCIeSerdesGetLaneStatus | ( | uint32_t | base_addr, |
uint32_t | lane_num | ||
) |
============================================================================
CSL_PCIeSerdesGetLaneStatus
Description
This API returns the status of the Lanes
Arguments base_addr, lane_num
Return Value CSL_SERDES_STATUS
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesGetLaneStatus(CSL_SRIO_SERDES_CFG_REGS, 0);
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CSL_IDEF_INLINE CSL_SERDES_STATUS CSL_PCIeSerdesGetMuxStatus | ( | uint32_t | base_addr, |
uint32_t | num_lanes | ||
) |
============================================================================
CSL_PCIeSerdesGetMuxStatus
Description
This API returns the status of the MUXed Serdes Lane PLL lock
Arguments base_addr, num_lanes
Return Value CSL_SERDES_STATUS
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
This API is applicable only for the case of MUXed SERDES (Example: K2L platform)
Example
CSL_PCIeSerdesGetMuxStatus(CSL_CSISC2_3_SERDES_CFG_REGS, 1);
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CSL_IDEF_INLINE CSL_SERDES_STATUS CSL_PCIeSerdesGetPLLStatus | ( | uint32_t | base_addr | ) |
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CSL_PCIeSerdesGetPLLStatus
Description
This API returns the status of the PLL lock
Arguments base_addr
Return Value CSL_SERDES_STATUS
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesGetPLLStatus(CSL_PCIE_SERDES_CFG_REGS);
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CSL_IDEF_INLINE CSL_SERDES_STATUS CSL_PCIeSerdesGetStatus | ( | uint32_t | base_addr, |
uint32_t | num_lanes | ||
) |
============================================================================
CSL_PCIeSerdesGetStatus
Description
This API returns the status of the PLL lock
Arguments base_addr, num_lanes
Return Value CSL_SERDES_STATUS
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesGetStatus(CSL_PCIE_SERDES_CFG_REGS, 1);
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CSL_IDEF_INLINE CSL_SERDES_RESULT CSL_PCIeSerdesInit | ( | uint32_t | base_addr, |
CSL_SERDES_REF_CLOCK | ref_clock, | ||
CSL_SERDES_LINK_RATE | rate | ||
) |
============================================================================
CSL_PCIeSerdesInit
Description
This API initializes the Serdes CMU and COMLANE registers.
Arguments base_addr, ref_clock, rate
Return Value CSL_SERDES_RESULT
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
csl_retval = CSL_PCIeSerdesInit(CSL_PCIE_SERDES_CFG_REGS, CSL_SERDES_REF_CLOCK_100M, CSL_SERDES_LINK_RATE_5G);
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CSL_IDEF_INLINE void CSL_PCIeSerdesLaneConfig | ( | uint32_t | base_addr, |
CSL_SERDES_REF_CLOCK | ref_clock, | ||
CSL_SERDES_LINK_RATE | rate, | ||
uint32_t | lane_num | ||
) |
============================================================================
CSL_PCIeSerdesLaneConfig
Description
This API configures the Serdes Lanes
Arguments base_addr, ref_clock, rate, lane_num
Return Value None
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesLaneConfig(CSL_PCIE_SERDES_CFG_REGS, CSL_SERDES_REF_CLOCK_100M, CSL_SERDES_LINK_RATE_5G, 1);
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CSL_IDEF_INLINE void CSL_PCIeSerdesLaneDisable | ( | uint32_t | base_addr, |
uint32_t | lane_num | ||
) |
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CSL_PCIeSerdesLaneDisable
Description
This API disables the Serdes Lanes
Arguments base_addr, lane_num
Return Value None
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesLaneDisable(CSL_PCIE_SERDES_CFG_REGS, 0);
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CSL_IDEF_INLINE void CSL_PCIeSerdesLaneEnable | ( | uint32_t | base_addr, |
uint32_t | num_lanes | ||
) |
============================================================================
CSL_PCIeSerdesLaneEnable
Description
This API enables the PCIE Lanes
Arguments base_addr, num_lanes
Return Value None
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesLaneEnable(CSL_PCIE_SLV_CFG_REGS, 1);
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CSL_IDEF_INLINE void CSL_PCIeSerdesLaneReset | ( | uint32_t | base_addr, |
uint32_t | lane_num | ||
) |
============================================================================
CSL_PCIeSerdesLaneReset
Description
This API resets the Serdes Lanes
Arguments base_addr, lane_num
Return Value None
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesLaneReset(CSL_PCIE_SERDES_CFG_REGS, 0);
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CSL_IDEF_INLINE void CSL_PCIeSerdesSetLaneRate | ( | uint32_t | base_addr, |
CSL_SERDES_PCIE_LANE_RATE | lane_ctrl_rate | ||
) |
============================================================================
CSL_PCIeSerdesSetLaneRate
Description
This API sets the Lane Rate for PCIE
Arguments base_addr, lane_ctrl_rate
Return Value None
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesSetLaneRate(CSL_PCIE_SLV_CFG_REGS, CSL_SERDES_PCIE_GEN_2);
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CSL_IDEF_INLINE void CSL_PCIeSerdesSetLoopback | ( | uint32_t | base_addr, |
uint32_t | lane_num, | ||
CSL_SERDES_LOOPBACK | loopback_mode | ||
) |
============================================================================
CSL_PCIeSerdesSetLoopback
Description
This API enables internal loopback and also brings the TX PLL out of reset
Arguments base_addr, lane_num, loopback_mode
Return Value None
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesSetLoopback(CSL_PCIE_SERDES_CFG_REGS, 0, CSL_SERDES_LOOPBACK_ENABLED);
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CSL_IDEF_INLINE void CSL_PCIeSerdesShutdown | ( | uint32_t | base_addr | ) |
============================================================================
CSL_PCIeSerdesShutdown
Description
This API shuts down the Serdes by Disabling and Resetting the Serdes
Arguments base_addr
Return Value None
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_PCIeSerdesShutdown(CSL_PCIE_SERDES_CFG_REGS);
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