Data Structures | Typedefs | Enumerations | Functions
CSL_SERDES

Data Structures

struct  CSL_SERDES_TBUS_DUMP
 SERDES PHY Test Bus Structure. More...
struct  CSL_SERDES_TAP_OFFSETS
 SERDES PHY Center DFE TAPs and Data Sample Comparators Structure. More...
struct  CSL_SERDES_SET_EQ_FLAG
 SERDES PHY DFE Set FLags Structure. More...
struct  CSL_SERDES_TX_COEFF
 SERDES PHY Transmitter Coefficients Structure. More...

Typedefs

typedef struct CSL_SERDES_TBUS_DUMP CSL_SERDES_TBUS_DUMP_T
 SERDES PHY Test Bus Structure.
typedef struct
CSL_SERDES_TAP_OFFSETS 
CSL_SERDES_TAP_OFFSETS_T
 SERDES PHY Center DFE TAPs and Data Sample Comparators Structure.
typedef struct
CSL_SERDES_SET_EQ_FLAG 
CSL_SERDES_SET_EQ_FLAG_T
 SERDES PHY DFE Set FLags Structure.
typedef struct CSL_SERDES_TX_COEFF CSL_SERDES_TX_COEFF_T
 SERDES PHY Transmitter Coefficients Structure.

Enumerations

enum  CSL_SERDES_REF_CLOCK {
  CSL_SERDES_REF_CLOCK_100M = 0, CSL_SERDES_REF_CLOCK_122p88M = 1, CSL_SERDES_REF_CLOCK_125M = 2, CSL_SERDES_REF_CLOCK_153p6M = 3,
  CSL_SERDES_REF_CLOCK_156p25M = 4, CSL_SERDES_REF_CLOCK_312p5M = 5
}
 SERDES REF CLOCK speed enumerators. More...
enum  CSL_SERDES_LINK_RATE {
  CSL_SERDES_LINK_RATE_1p25G = 0, CSL_SERDES_LINK_RATE_4p9152G = 1, CSL_SERDES_LINK_RATE_5G = 2, CSL_SERDES_LINK_RATE_6p144G = 3,
  CSL_SERDES_LINK_RATE_6p25G = 4, CSL_SERDES_LINK_RATE_7p3728G = 5, CSL_SERDES_LINK_RATE_9p8304G = 6, CSL_SERDES_LINK_RATE_10G = 7,
  CSL_SERDES_LINK_RATE_10p3125G = 8, CSL_SERDES_LINK_RATE_12p5G = 9
}
 SERDES LINK RATE speed enumerators. More...
enum  CSL_SERDES_LOOPBACK { CSL_SERDES_LOOPBACK_ENABLED = 0, CSL_SERDES_LOOPBACK_DISABLED = 1 }
 SERDES LOOPBACK enumerators. More...
enum  CSL_SERDES_STATUS { CSL_SERDES_STATUS_PLL_NOT_LOCKED = 0, CSL_SERDES_STATUS_PLL_LOCKED = 1 }
 SERDES PLL STATUS enumerators. More...
enum  CSL_SERDES_RESULT { CSL_SERDES_NO_ERR = 0, CSL_SERDES_INVALID_REF_CLOCK = 1, CSL_SERDES_INVALID_LANE_RATE = 2 }
 SERDES INIT RETURN VALUE enumerators. More...
enum  CSL_SERDES_LANE_CTRL_RATE { CSL_SERDES_LANE_FULL_RATE = 0, CSL_SERDES_LANE_HALF_RATE = 1, CSL_SERDES_LANE_QUARTER_RATE = 2 }
 SERDES LANE CTRL TX/RX RATE enumerators. More...
enum  CSL_SERDES_LANE_ENABLE_STATUS { CSL_SERDES_LANE_ENABLE_NO_ERR = 0, CSL_SERDES_LANE_ENABLE_INVALID_RATE = 1 }
 SERDES LANE CTRL STATUS enumerators. More...
enum  csl_serdes_phy_type {
  SERDES_10GE = 0, SERDES_AIF2_B8 = 1, SERDES_AIF2_B4 = 2, SERDES_SRIO = 3,
  SERDES_PCIe = 4, SERDES_HYPERLINK = 5, SERDES_SGMII = 6, SERDES_DFE = 7,
  SERDES_IQN = 8
}
 SERDES PHY TYPE enumerators. More...

Functions

CSL_IDEF_INLINE void CSL_SerdesWriteTbusAddr (uint32_t base_addr, int32_t iSelect, int32_t iOffset)
CSL_IDEF_INLINE uint32_t CSL_SerdesReadTbusVal (uint32_t base_addr)
CSL_IDEF_INLINE uint32_t CSL_SerdesReadSelectedTbus (uint32_t base_addr, int32_t iSelect, int32_t iOffset)
CSL_IDEF_INLINE void csl_serdes_tbus_dump (uint32_t base_addr, CSL_SERDES_TBUS_DUMP_T *pTbusDump, csl_serdes_phy_type phy_type)
CSL_IDEF_INLINE void CSL_SERDES_CONFIG_CM_C1_C2 (uint32_t base_addr, uint32_t lane_num, uint32_t CMcoeff, uint32_t C1coeff, uint32_t C2coeff, csl_serdes_phy_type phy_type)
CSL_IDEF_INLINE CSL_SERDES_RESULT CSL_Serdes_Deassert_Reset (uint32_t base_addr, csl_serdes_phy_type phy_type, uint32_t isBlock, uint32_t num_lanes)
CSL_IDEF_INLINE void CSL_Serdes_Assert_Reset (uint32_t base_addr, csl_serdes_phy_type phy_type)
CSL_IDEF_INLINE void CSL_SerdesGetAverageOffsets (uint32_t base_addr, uint32_t num_lanes, csl_serdes_phy_type phy_type, CSL_SERDES_TAP_OFFSETS_T *pTapOffsets)
CSL_IDEF_INLINE void CSL_Serdes_Override_Cmp_Tap_Offsets (uint32_t base_addr, uint32_t lane_num, uint32_t comp_no, CSL_SERDES_TAP_OFFSETS_T *pTapOffsets)
CSL_IDEF_INLINE void CSL_Serdes_Override_Cmp_Tap_Offsets_CDFE (uint32_t base_addr, uint32_t lane_num, uint32_t fsm_select, uint32_t comp_no, CSL_SERDES_TAP_OFFSETS_T *pTapOffsets)
CSL_IDEF_INLINE void CSL_SerdesWriteAverageOffsets (uint32_t base_addr, uint32_t num_lanes, csl_serdes_phy_type phy_type, CSL_SERDES_TAP_OFFSETS_T *pTapOffsets)
CSL_IDEF_INLINE void CSL_SerdesTXRXSetEqualizer (uint32_t base_addr, uint32_t num_lanes, csl_serdes_phy_type phy_type, CSL_SERDES_SET_EQ_FLAG_T set_eq_flags)
CSL_IDEF_INLINE void CSL_Serdes_DFE_OffsetCalibration (uint32_t base_addr, uint32_t num_lanes, csl_serdes_phy_type phy_type, CSL_SERDES_TX_COEFF_T tx_coeff)

Detailed Description

============================================================================

Introduction

Overview

This is the top level SERDES API with enumerations for various supported reference clocks, link rates, lane control rates across different modules.

References

============================================================================


Typedef Documentation

SERDES PHY DFE Set FLags Structure.

============================================================================

SERDES PHY Center DFE TAPs and Data Sample Comparators Structure.

============================================================================

SERDES PHY Test Bus Structure.

============================================================================

SERDES PHY Transmitter Coefficients Structure.

============================================================================


Enumeration Type Documentation

SERDES LANE CTRL TX/RX RATE enumerators.

============================================================================

Enumerator:
CSL_SERDES_LANE_FULL_RATE 

SERDES Full Rate

CSL_SERDES_LANE_HALF_RATE 

SERDES Half Rate

CSL_SERDES_LANE_QUARTER_RATE 

SERDES Quarter Rate

SERDES LANE CTRL STATUS enumerators.

============================================================================

Enumerator:
CSL_SERDES_LANE_ENABLE_NO_ERR 

Lane Control Enable Success

CSL_SERDES_LANE_ENABLE_INVALID_RATE 

Invalid Lane Control Rate

SERDES LINK RATE speed enumerators.

============================================================================

Enumerator:
CSL_SERDES_LINK_RATE_1p25G 

1.25 GHz

CSL_SERDES_LINK_RATE_4p9152G 

4.9152 GHz

CSL_SERDES_LINK_RATE_5G 

5 GHz

CSL_SERDES_LINK_RATE_6p144G 

6.144 GHz

CSL_SERDES_LINK_RATE_6p25G 

6.25 GHz

CSL_SERDES_LINK_RATE_7p3728G 

7.3728 GHz

CSL_SERDES_LINK_RATE_9p8304G 

9.8304 GHz

CSL_SERDES_LINK_RATE_10G 

10 GHz

CSL_SERDES_LINK_RATE_10p3125G 

10.3125 GHz

CSL_SERDES_LINK_RATE_12p5G 

12.5 GHz

SERDES LOOPBACK enumerators.

============================================================================

Enumerator:
CSL_SERDES_LOOPBACK_ENABLED 

Loopback Enabled

CSL_SERDES_LOOPBACK_DISABLED 

Loopback Disabled

SERDES PHY TYPE enumerators.

============================================================================

Enumerator:
SERDES_10GE 

10GE SERDES

SERDES_AIF2_B8 

AIF2 B8 SERDES

SERDES_AIF2_B4 

AIF2 B4 SERDES

SERDES_SRIO 

SRIO SERDES

SERDES_PCIe 

PCIe SERDES

SERDES_HYPERLINK 

Hyperlink SERDES

SERDES_SGMII 

SGMII SERDES

SERDES_DFE 

DFE SERDES

SERDES_IQN 

IQN SERDES

SERDES REF CLOCK speed enumerators.

============================================================================
CSL_SERDES_REF_CLOCK

Enumerator:
CSL_SERDES_REF_CLOCK_100M 

100 MHz

CSL_SERDES_REF_CLOCK_122p88M 

122.8 MHz

CSL_SERDES_REF_CLOCK_125M 

125 MHz

CSL_SERDES_REF_CLOCK_153p6M 

153.6 MHz

CSL_SERDES_REF_CLOCK_156p25M 

156.25 MHz

CSL_SERDES_REF_CLOCK_312p5M 

312.5 MHz

SERDES INIT RETURN VALUE enumerators.

============================================================================

Enumerator:
CSL_SERDES_NO_ERR 

Init Success

CSL_SERDES_INVALID_REF_CLOCK 

Invalid Reference Clock

CSL_SERDES_INVALID_LANE_RATE 

Invalid Lane Rate

SERDES PLL STATUS enumerators.

============================================================================

Enumerator:
CSL_SERDES_STATUS_PLL_NOT_LOCKED 

PLL Not Locked

CSL_SERDES_STATUS_PLL_LOCKED 

PLL Locked


Function Documentation

CSL_IDEF_INLINE void CSL_Serdes_Assert_Reset ( uint32_t  base_addr,
csl_serdes_phy_type  phy_type 
)

============================================================================
CSL_Serdes_Assert_Reset

Description
Function to assert reset on the SERDES PHY

Arguments

        base_addr       Serdes IP base address
        phy_type        Serdes PHY type enumerator
 *
 *   <b> Return Value  </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim

    

===========================================================================

CSL_IDEF_INLINE void CSL_SERDES_CONFIG_CM_C1_C2 ( uint32_t  base_addr,
uint32_t  lane_num,
uint32_t  CMcoeff,
uint32_t  C1coeff,
uint32_t  C2coeff,
csl_serdes_phy_type  phy_type 
)

============================================================================
CSL_SERDES_CONFIG_CM_C1_C2

Description
This API is used for configuring the Serdes Transmitter CM, C1, C2 coefficients.

Arguments

        base_addr                   Serdes IP base address
        lane_num                    Serdes lane number configured
        CMcoeff, C1coeff, C2coeff   Transmit Pre & Post Cursor De-Emphasis values
        phy_type                    Serdes PHY type enumerator
 *
 *   <b> Return Value  </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim

     CSL_SERDES_CONFIG_CM_C1_C2(CSL_HYPERLINK_0_SERDES_CFG_REGS, 0, 6, 3, 2,
     SERDES_HYPERLINK);

    

===========================================================================

CSL_IDEF_INLINE CSL_SERDES_RESULT CSL_Serdes_Deassert_Reset ( uint32_t  base_addr,
csl_serdes_phy_type  phy_type,
uint32_t  isBlock,
uint32_t  num_lanes 
)

============================================================================
CSL_Serdes_Deassert_Reset

Description
Function to de-assert reset on the SERDES PHY

Arguments

        base_addr       Serdes IP base address
        phy_type        Serdes PHY type enumerator
        isBlock         Waits for LANE OK to complete after deasserting the reset
        num_lanes       Number of lanes configured
 *
 *   <b> Return Value  </b>
 *   @n  Returns CSL_SERDES_RESULT
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim

    

===========================================================================

CSL_IDEF_INLINE void CSL_Serdes_DFE_OffsetCalibration ( uint32_t  base_addr,
uint32_t  num_lanes,
csl_serdes_phy_type  phy_type,
CSL_SERDES_TX_COEFF_T  tx_coeff 
)

============================================================================
CSL_Serdes_DFE_OffsetCalibration

Description
This API calibrates the Serdes DFE by finding the averaging offsets & applies the offset compensation patch to the CDFE

Arguments

        base_addr   Serdes IP base address
        num_lanes   Number of lanes to be configured
        phy_type    Serdes PHY enumerator
        tx_coeff    Transmit Coefficients structure

 *   <b> Return Value  </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n None
 *
 *   @b Example
 *   @verbatim

 CSL_Serdes_DFE_OffsetCalibration(CSL_XGE_SERDES_CFG_REGS, 2, SERDES_10GE, tx_coeff);

    

===========================================================================

CSL_IDEF_INLINE void CSL_Serdes_Override_Cmp_Tap_Offsets ( uint32_t  base_addr,
uint32_t  lane_num,
uint32_t  comp_no,
CSL_SERDES_TAP_OFFSETS_T pTapOffsets 
)

============================================================================
CSL_Serdes_Override_Cmp_Tap_Offsets

Description
Force Serdes comparator and tap offsets to override value

Arguments

        base_addr       Serdes IP base address
        lane_num        Lane Number to be configured
        comp_no         Comparator number overriden
        *pTapOffsets    Pointer to the tap offsets structure
 *
 *   <b> Return Value  </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim
 *
 *   CSL_Serdes_Override_Cmp_Tap_Offsets(base_addr, lane_num,comp_no, pTapOffsets);

    

===========================================================================

CSL_IDEF_INLINE void CSL_Serdes_Override_Cmp_Tap_Offsets_CDFE ( uint32_t  base_addr,
uint32_t  lane_num,
uint32_t  fsm_select,
uint32_t  comp_no,
CSL_SERDES_TAP_OFFSETS_T pTapOffsets 
)

============================================================================
CSL_Serdes_Override_Cmp_Tap_Offsets_CDFE

Description
Force Serdes comparator and tap offsets to override value for CDFE adaptation

Arguments

        base_addr       Serdes IP base address
        lane_num        Lane Number to be configured
        fsm_select      Comparator FSM select field
        comp_no         Comparator number overriden for CDFE adaptation
        *pTapOffsets    Pointer to the tap offsets structure
 *
 *   <b> Return Value  </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim
 *
 *  CSL_Serdes_Override_Cmp_Tap_Offsets_CDFE(base_addr, lane_num, fsm_select, comp_no, pTapOffsets);

    

===========================================================================

CSL_IDEF_INLINE void csl_serdes_tbus_dump ( uint32_t  base_addr,
CSL_SERDES_TBUS_DUMP_T pTbusDump,
csl_serdes_phy_type  phy_type 
)

============================================================================
csl_serdes_tbus_dump

Description
Function to read out the entire TBUS

Arguments

        base_addr     Serdes IP base address
        *pTbusDump    Pointer to the array structure for storing the tbus values
        phy_type      Serdes PHY type enumerator
 *
 *   <b> Return Value  </b>
 *   @n  Returns
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim

    

===========================================================================

CSL_IDEF_INLINE void CSL_SerdesGetAverageOffsets ( uint32_t  base_addr,
uint32_t  num_lanes,
csl_serdes_phy_type  phy_type,
CSL_SERDES_TAP_OFFSETS_T pTapOffsets 
)

============================================================================
CSL_SerdesGetAverageOffsets

Description
Function to calculate the Serdes average comparator/tap offset values

Arguments

        base_addr       Serdes IP base address
        num_lanes       Number of Lanes to be configured
        phy_type        Serdes PHY type enumerator
        *pTapOffsets    Pointer to the tap offsets structure to store the
                        average DFE offset values
 *
 *   <b> Return Value  </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim
 *
 *   CSL_SerdesGetAverageOffsets(base_addr, num_lanes, phy_type, &pTapOffsets);

    

===========================================================================

CSL_IDEF_INLINE uint32_t CSL_SerdesReadSelectedTbus ( uint32_t  base_addr,
int32_t  iSelect,
int32_t  iOffset 
)

============================================================================
CSL_SerdesReadSelectedTbus

Description
Function to read out selected 8-bit TBUS value

Arguments

        base_addr     Serdes IP base address
        iSelect       To select the specific Test Bus based on the PHY type
        iOffset       To write the specific offset address in the TBUS
 *
 *   <b> Return Value  </b>
 *   @n  Returns 8-bit TBUS field value
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim

    

===========================================================================

CSL_IDEF_INLINE uint32_t CSL_SerdesReadTbusVal ( uint32_t  base_addr)

============================================================================
CSL_SerdesReadTbusVal

Description
Function to read the Serdes Test Bus (tbus) value

Arguments

        base_addr     Serdes IP base address
 *
 *   <b> Return Value  </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim

    

===========================================================================

CSL_IDEF_INLINE void CSL_SerdesTXRXSetEqualizer ( uint32_t  base_addr,
uint32_t  num_lanes,
csl_serdes_phy_type  phy_type,
CSL_SERDES_SET_EQ_FLAG_T  set_eq_flags 
)

============================================================================
CSL_SerdesTXSetEqualizer

Description
This API sets the Serdes TX Output Swing Voltage and Center DFE values

Arguments

        base_addr      Serdes IP base address
        num_lanes      Number of lanes to be configured
        phy_type       Serdes PHY enumerator
        tx_coeff       Transmit Coefficients structure
        set_eq_flags   Structure to set the Equalizer Flags (Voltage Regulator,
                       CDFE Enable and Offset Compensation Enable)
 *
 *   <b> Return Value  </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n None
 *
 *   @b Example
 *   @verbatim

     CSL_SerdesTXSetEqualizer(CSL_XGE_SERDES_CFG_REGS, 2, SERDES_10GE, set_eq_flags);

    

===========================================================================

CSL_IDEF_INLINE void CSL_SerdesWriteAverageOffsets ( uint32_t  base_addr,
uint32_t  num_lanes,
csl_serdes_phy_type  phy_type,
CSL_SERDES_TAP_OFFSETS_T pTapOffsets 
)

============================================================================
CSL_SerdesWriteAverageOffsets

Description
Function to write out the average RX comparator offsets during every SERDES initialization

Arguments

        base_addr       Serdes IP base address
        num_lanes       Number of lanes to be configured
        phy_type        Serdes PHY enumerator
        *pTapOffsets    Pointer to the tap offsets structure
 *
 *   <b> Return Value  </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim
 *
 *   CSL_SerdesWriteAverageOffsets(base_addr, num_lanes, phy_type, &pTapOffsets);

    

===========================================================================

CSL_IDEF_INLINE void CSL_SerdesWriteTbusAddr ( uint32_t  base_addr,
int32_t  iSelect,
int32_t  iOffset 
)

============================================================================
CSL_SerdesWriteTbusAddr

Description
Function to write to the Serdes Test Bus Address

Arguments

        base_addr     Serdes IP base address
        iSelect       To select the specific Test Bus based on the PHY type
        iOffset       To write the specific offset address in the TBUS
 *
 *   <b> Return Value  </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Reads
 *   @n None
 *
 *  <b> Usage Constraints: </b>
 *  @n  None
 *
 *   @b Example
 *   @verbatim

    

===========================================================================


Copyright 2014, Texas Instruments Incorporated