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CSL_CPSW_PORTSTAT | Holds Port Statistics Enable register contents |
CSL_CPSW_STATS | Holds the EMAC statistics |
CSL_CPSW_TSCNTL | Holds Port Time Sync Control register contents |
CSL_IntcContext | |
CSL_IntcDropStatus | |
CSL_IntcEventHandlerRecord | |
CSL_IntcObj | |
CSL_SERDES_SET_EQ_FLAG | SERDES PHY DFE Set FLags Structure |
CSL_SERDES_TAP_OFFSETS | SERDES PHY Center DFE TAPs and Data Sample Comparators Structure |
CSL_SERDES_TBUS_DUMP | SERDES PHY Test Bus Structure |
CSL_SERDES_TX_COEFF | SERDES PHY Transmitter Coefficients Structure |
EMIF4_ECC_CONTROL | ECC Control |
EMIF4_MSTID_COS_MAPPING | Master ID to COS Mapping |
EMIF4_PRI_COS_MAPPING | Priority to COS Mapping |
EMIF4F_IODFT_CONTROL | IODFT Control Values |
EMIF4F_OUTPUT_IMP_CONFIG | SDRAM Output Impedance Calibration Configuation |
EMIF4F_PERF_CONFIG | Performance Counter Configuration |
EMIF4F_PWR_MGMT_CONFIG | Power Management Configuration |
EMIF4F_SDRAM_CONFIG | EMIF4F SDRAM Configuration |
EMIF4F_TIMING1_CONFIG | EMIF4F Timing1 Configuration |
EMIF4F_VBUS_CONFIG_VALUE | VBUS Configuration Values |