Data Fields
pciePMCapCtlStatReg_s Struct Reference

Specification of the Power Management Capabilities Control and Status Register. More...

#include <pcie.h>

Data Fields

uint32_t raw
 [ro] Raw image of register on read; actual value on write
uint8_t dataReg
 [ro] Data register for additional information. Not supported.
uint8_t clkCtrlEn
 [ro] Bus Power/Clock Control Enable. Hardwired to zero.
uint8_t b2b3Support
 [ro] B2 and B3 support. Hardwired to zero.
uint8_t pmeStatus
 [rw] PME Status. Indicates if a previously enabled PME event occurred or not.
uint8_t dataScale
 [ro] Data Scale. Not supported.
uint8_t dataSelect
 [ro] Data Select. Not supported.
uint8_t pmeEn
 [rw] PME Enable. Value of 1 indicates device is enabled to generate PME.
uint8_t noSoftRst
 [rw] No Soft Reset.
uint8_t pwrState
 [rw] Power State.

Detailed Description

Specification of the Power Management Capabilities Control and Status Register.

This register may be used for both endpoint and root complex modes.


Field Documentation

[ro] B2 and B3 support. Hardwired to zero.

Field size: 1 bits

[ro] Bus Power/Clock Control Enable. Hardwired to zero.

Field size: 1 bits

[ro] Data register for additional information. Not supported.

Field size: 8 bits

[ro] Data Scale. Not supported.

Field size: 2 bits

[ro] Data Select. Not supported.

Field size: 4 bits

[rw] No Soft Reset.

It is set to disable reset during a transition from D3 to D0.

Field size: 1 bits

[rw] PME Enable. Value of 1 indicates device is enabled to generate PME.

Field size: 1 bits

[rw] PME Status. Indicates if a previously enabled PME event occurred or not.

Write 1 to clear.

Field size: 1 bits

[rw] Power State.

Controls the device power state. Writes are ignored if the state is not supported. 0 = D0 power state 1h = D1 power state 2h = D2 power state 3h = D3 power states

Field size: 2 bits


The documentation for this struct was generated from the following file:

Copyright 2014, Texas Instruments Incorporated