Data Fields
pcieType1BridgeIntReg_s Struct Reference

Specification of the Bridge Control and Interrupt Register. More...

#include <pcie.h>

Data Fields

uint32_t raw
 [ro] Raw image of register on read; actual value on write
uint8_t serrEnStatus
 [ro] Discard Timer SERR Enable Status.
uint8_t timerStatus
 [ro] Discard Timer Status.
uint8_t secTimer
 [ro] Secondary Discard Timer.
uint8_t priTimer
 [ro] Primary Discard Timer.
uint8_t b2bEn
 [ro] Fast Back to Back Transactions Enable.
uint8_t secBusRst
 [rw] Secondary Bus Reset.
uint8_t mstAbortMode
 [ro] Master Abort Mode.
uint8_t vgaDecode
 [rw] VGA 16 bit Decode
uint8_t vgaEn
 [rw] VGA Enable
uint8_t isaEn
 [rw] ISA Enable
uint8_t serrEn
 [rw] SERR Enable.
uint8_t pErrRespEn
 [rw] Parity Error Response Enable.
uint8_t intPin
 [rw] Interrupt Pin.
uint8_t intLine
 [rw] Interrupt Line. Value is system software specified.

Detailed Description

Specification of the Bridge Control and Interrupt Register.


Field Documentation

[ro] Fast Back to Back Transactions Enable.

Not applicable to PCI Express. Hardwired to 0.

Field size: 1 bit

[rw] Interrupt Line. Value is system software specified.

Field size: 8 bits

[rw] Interrupt Pin.

It identifies the legacy interrupt message that the device uses. For single function configuration, the core only uses INTA. This register is writable through internal bus interface.

0 = Legacy interrupt is not being used 1h = INTA 2h = INTB 3h = INTC 4h = INTD Others = Reserved.

Field size: 8 bits

[rw] ISA Enable

Field size: 1 bit

[ro] Master Abort Mode.

Not applicable to PCI Express. Hardwired to 0.

Field size: 1 bit

[rw] Parity Error Response Enable.

This bit controls the logging of poisoned TLPs in pcieType1SecStatReg_s::mstDPErr

Field size: 1 bit

[ro] Primary Discard Timer.

Not applicable to PCI Express. Hardwired to 0.

Field size: 1 bit

[rw] Secondary Bus Reset.

Field size: 1 bit

[ro] Secondary Discard Timer.

Not applicable to PCI Express. Hardwired to 0.

Field size: 1 bit

[rw] SERR Enable.

Set to enable forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL messages.

Field size: 1 bit

[ro] Discard Timer SERR Enable Status.

Not Applicable to PCI Express. Hardwired to 0.

Field size: 1 bit

[ro] Discard Timer Status.

Not applicable to PCI Express. Hardwired to 0.

Field size: 1 bit

[rw] VGA 16 bit Decode

Field size: 1 bit

[rw] VGA Enable

Field size: 1 bit


The documentation for this struct was generated from the following file:

Copyright 2014, Texas Instruments Incorporated