Enumerations |
enum | CSL_SERDES_REF_CLOCK {
CSL_SERDES_REF_CLOCK_100M = 0,
CSL_SERDES_REF_CLOCK_122p88M = 1,
CSL_SERDES_REF_CLOCK_125M = 2,
CSL_SERDES_REF_CLOCK_153p6M = 3,
CSL_SERDES_REF_CLOCK_156p25M = 4,
CSL_SERDES_REF_CLOCK_312p5M = 5
} |
| SERDES REF CLOCK speed enumerators. More...
|
enum | CSL_SERDES_LINK_RATE {
CSL_SERDES_LINK_RATE_1p25G = 0,
CSL_SERDES_LINK_RATE_4p9152G = 1,
CSL_SERDES_LINK_RATE_5G = 2,
CSL_SERDES_LINK_RATE_6p144G = 3,
CSL_SERDES_LINK_RATE_6p25G = 4,
CSL_SERDES_LINK_RATE_10G = 5,
CSL_SERDES_LINK_RATE_10p3125G = 6,
CSL_SERDES_LINK_RATE_12p5G = 7
} |
| SERDES LINK RATE speed enumerators. More...
|
enum | CSL_SERDES_LOOPBACK { CSL_SERDES_LOOPBACK_ENABLED = 0,
CSL_SERDES_LOOPBACK_DISABLED = 1
} |
| SERDES LOOPBACK enumerators. More...
|
enum | CSL_SERDES_STATUS { CSL_SERDES_STATUS_PLL_NOT_LOCKED = 0,
CSL_SERDES_STATUS_PLL_LOCKED = 1
} |
| SERDES PLL STATUS enumerators. More...
|
enum | CSL_SERDES_RESULT { CSL_SERDES_NO_ERR = 0,
CSL_SERDES_INVALID_REF_CLOCK = 1,
CSL_SERDES_INVALID_LANE_RATE = 2
} |
| SERDES INIT RETURN VALUE enumerators. More...
|
enum | CSL_SERDES_LANE_CTRL_RATE { CSL_SERDES_LANE_FULL_RATE = 0,
CSL_SERDES_LANE_HALF_RATE = 1,
CSL_SERDES_LANE_QUARTER_RATE = 2
} |
| SERDES LANE CTRL TX/RX RATE enumerators. More...
|
enum | CSL_SERDES_LANE_ENABLE_STATUS { CSL_SERDES_LANE_ENABLE_NO_ERR = 0,
CSL_SERDES_LANE_ENABLE_INVALID_RATE = 1
} |
| SERDES LANE CTRL STATUS enumerators. More...
|
enum | csl_serdes_phy_type {
SERDES_10GE = 0,
SERDES_AIF2_B8 = 1,
SERDES_AIF2_B4 = 2,
SERDES_SRIO = 3,
SERDES_PCIe = 4,
SERDES_HYPERLINK = 5,
SERDES_SGMII = 6,
SERDES_DFE = 7,
SERDES_IQN = 8
} |
| SERDES PHY TYPE enumerators. More...
|
Functions |
CSL_IDEF_INLINE void | CSL_SERDES_CONFIG_CM_C1_C2 (uint32_t base_addr, uint32_t lane_num, uint32_t CMcoeff, uint32_t C1coeff, uint32_t C2coeff, csl_serdes_phy_type phy_type) |
Detailed Description
============================================================================
Introduction
Overview
This is the top level SERDES API with enumerations for various supported reference clocks, link rates, lane control rates across different modules.
References
============================================================================
Enumeration Type Documentation
SERDES LANE CTRL TX/RX RATE enumerators.
============================================================================
- Enumerator:
CSL_SERDES_LANE_FULL_RATE |
SERDES Full Rate
|
CSL_SERDES_LANE_HALF_RATE |
SERDES Half Rate
|
CSL_SERDES_LANE_QUARTER_RATE |
SERDES Quarter Rate
|
SERDES LANE CTRL STATUS enumerators.
============================================================================
- Enumerator:
CSL_SERDES_LANE_ENABLE_NO_ERR |
Lane Control Enable Success
|
CSL_SERDES_LANE_ENABLE_INVALID_RATE |
Invalid Lane Control Rate
|
SERDES LINK RATE speed enumerators.
============================================================================
- Enumerator:
CSL_SERDES_LINK_RATE_1p25G |
1.25 GHz
|
CSL_SERDES_LINK_RATE_4p9152G |
4.9152 GHz
|
CSL_SERDES_LINK_RATE_5G |
5 GHz
|
CSL_SERDES_LINK_RATE_6p144G |
6.144 GHz
|
CSL_SERDES_LINK_RATE_6p25G |
6.25 GHz
|
CSL_SERDES_LINK_RATE_10G |
10 GHz
|
CSL_SERDES_LINK_RATE_10p3125G |
10.3125 GHz
|
CSL_SERDES_LINK_RATE_12p5G |
12.5 GHz
|
SERDES LOOPBACK enumerators.
============================================================================
- Enumerator:
CSL_SERDES_LOOPBACK_ENABLED |
Loopback Enabled
|
CSL_SERDES_LOOPBACK_DISABLED |
Loopback Disabled
|
SERDES PHY TYPE enumerators.
============================================================================
- Enumerator:
SERDES_10GE |
10GE SERDES
|
SERDES_AIF2_B8 |
AIF2 B8 SERDES
|
SERDES_AIF2_B4 |
AIF2 B4 SERDES
|
SERDES_SRIO |
SRIO SERDES
|
SERDES_PCIe |
PCIe SERDES
|
SERDES_HYPERLINK |
Hyperlink SERDES
|
SERDES_SGMII |
SGMII SERDES
|
SERDES_DFE |
DFE SERDES
|
SERDES_IQN |
IQN SERDES
|
SERDES REF CLOCK speed enumerators.
============================================================================
CSL_SERDES_REF_CLOCK
- Enumerator:
CSL_SERDES_REF_CLOCK_100M |
100 MHz
|
CSL_SERDES_REF_CLOCK_122p88M |
122.8 MHz
|
CSL_SERDES_REF_CLOCK_125M |
125 MHz
|
CSL_SERDES_REF_CLOCK_153p6M |
153.6 MHz
|
CSL_SERDES_REF_CLOCK_156p25M |
156.25 MHz
|
CSL_SERDES_REF_CLOCK_312p5M |
312.5 MHz
|
SERDES INIT RETURN VALUE enumerators.
============================================================================
- Enumerator:
CSL_SERDES_NO_ERR |
Init Success
|
CSL_SERDES_INVALID_REF_CLOCK |
Invalid Reference Clock
|
CSL_SERDES_INVALID_LANE_RATE |
Invalid Lane Rate
|
SERDES PLL STATUS enumerators.
============================================================================
- Enumerator:
CSL_SERDES_STATUS_PLL_NOT_LOCKED |
PLL Not Locked
|
CSL_SERDES_STATUS_PLL_LOCKED |
PLL Locked
|
Function Documentation
============================================================================
CSL_SERDES_CONFIG_CM_C1_C2
Description
This API is used for configuring the CM, C1, C2 coefficients.
Arguments base_addr, lane_num, CMcoeff, C1coeff, C2coeff, phy_type
Return Value
None
Pre Condition
None
Post Condition
None
Reads
None
Usage Constraints:
None
Example
CSL_SERDES_CONFIG_CM_C1_C2(CSL_HYPERLINK_0_SERDES_CFG_REGS, 0, 6, 3, 2, SERDES_HYPERLINK);
===========================================================================