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Specification of the PCS Configuration 0 Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
[ro] Raw image of register on read; actual value on write | |
uint8_t | pcsSync |
[rw] Receiver lock/sync control. | |
uint8_t | pcsHoldOff |
[rw] Receiver initialization holdoff control. | |
uint8_t | pcsRCDelay |
[rw] Rate change delay. | |
uint8_t | pcsDetDelay |
[rw] Detection delay. | |
uint8_t | pcsShrtTM |
[rw] Enable short times for debug purposes. | |
uint8_t | pcsStat186 |
[rw] Enable PIPE Spec 1.86 for phystatus behavior. | |
uint8_t | pcsFixTerm |
[rw] Fed term output to 3'b100 during reset. | |
uint8_t | pcsFixStd |
[rw] Fix std output to 2'b10. | |
uint8_t | pcsL2EnidlOff |
[rw] Deassert enidl during L2 state. | |
uint8_t | pcsL2L0SRxOff |
[rw] Deassert Rx enable in L0s state. | |
uint8_t | pcsRxTxOn |
[rw] RX and TX on during reset and TX also on in P1 state. | |
uint8_t | pcsRxTxRst |
[rw] RX and TX on during reset. |
Specification of the PCS Configuration 0 Register.
uint8_t pciePcsCfg0Reg_s::pcsDetDelay |
[rw] Detection delay.
Field size: 4 bits
uint8_t pciePcsCfg0Reg_s::pcsFixStd |
[rw] Fix std output to 2'b10.
Field size: 1 bits
uint8_t pciePcsCfg0Reg_s::pcsFixTerm |
[rw] Fed term output to 3'b100 during reset.
Field size: 1 bits
uint8_t pciePcsCfg0Reg_s::pcsHoldOff |
[rw] Receiver initialization holdoff control.
Field size: 8 bits
uint8_t pciePcsCfg0Reg_s::pcsL2EnidlOff |
[rw] Deassert enidl during L2 state.
Field size: 1 bits
uint8_t pciePcsCfg0Reg_s::pcsL2L0SRxOff |
[rw] Deassert Rx enable in L0s state.
Field size: 1 bits
uint8_t pciePcsCfg0Reg_s::pcsRCDelay |
[rw] Rate change delay.
Field size: 2 bits
uint8_t pciePcsCfg0Reg_s::pcsRxTxOn |
[rw] RX and TX on during reset and TX also on in P1 state.
Field size: 1 bits
uint8_t pciePcsCfg0Reg_s::pcsRxTxRst |
[rw] RX and TX on during reset.
Field size: 1 bits
uint8_t pciePcsCfg0Reg_s::pcsShrtTM |
[rw] Enable short times for debug purposes.
Field size: 1 bits
uint8_t pciePcsCfg0Reg_s::pcsStat186 |
[rw] Enable PIPE Spec 1.86 for phystatus behavior.
Field size: 1 bits
uint8_t pciePcsCfg0Reg_s::pcsSync |
[rw] Receiver lock/sync control.
Field size: 5 bits