Data Fields
pcieLaneSkewReg_s Struct Reference

Specification of the Lane Skew register. More...

#include <pcie.h>

Data Fields

uint32_t raw
uint8_t l2Deskew
 [rw] Set to Disable Lane to Lane Deskew.
uint8_t ackDisable
 [rw] Set to disable Ack and Nak DLLP transmission.
uint8_t fcDisable
 [rw] Set to disable transmission of Flow Control DLLPs.
uint32_t laneSkew
 [rw] Insert Lane Skew for Transmit.

Detailed Description

Specification of the Lane Skew register.

This register may be used for both endpoint and root complex modes.


Field Documentation

[rw] Set to disable Ack and Nak DLLP transmission.

Field size: 1 bit

[rw] Set to disable transmission of Flow Control DLLPs.

Field size: 1 bit

[rw] Set to Disable Lane to Lane Deskew.

Field size: 1 bit

[rw] Insert Lane Skew for Transmit.

The value is in units of one symbol time. Thus a value 0x02 will force a skew of two symbol times for that lane. Max allowed is 5 symbol times. This 24 bit field is used for programming skew for eight lanes with three bits per lane.

Field size: 24 bits

[ro] Raw image of register on read; actual value on write


The documentation for this struct was generated from the following file:

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