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Specification of the Link Status and Control Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
uint8_t | linkBwStatus |
[rw] Link Autonomous Bandwidth Status. | |
uint8_t | linkBwMgmtStatus |
[rw] Link Bandwidth Management Status. | |
uint8_t | dllActive |
[rw] Data Link Layer Active | |
uint8_t | slotClkCfg |
[rw] Slot Clock Configuration. Writable from internal bus interface. | |
uint8_t | linkTraining |
[rw] Link Training. Not applicable to EP. | |
uint8_t | undef |
[rw] Undefined for PCI Express. | |
uint8_t | negotiatedLinkWd |
[rw] Negotiated Link Width. Set automatically by hardware after link initialization. | |
uint8_t | linkSpeed |
[rw] Link Speed. Set automatically by hardware after link initialization. | |
uint8_t | linkBwIntEn |
[rw] Link Autonomous Bandwidth Interrupt Enable. Not applicable and is reserved for EP | |
uint8_t | linkBwMgmtIntEn |
[rw] Link Bandwidth Management Interrupt Enable. Not applicable and is reserved for EP. | |
uint8_t | hwAutoWidthDis |
[rw] Hardware Autonomous Width Disable. Not supported and hardwired to zero. | |
uint8_t | clkPwrMgmtEn |
[rw] Enable Clock Power Management. | |
uint8_t | extSync |
[rw] Extended Synchronization. | |
uint8_t | commonClkCfg |
[rw] Common Clock Configuration. | |
uint8_t | retrainLink |
[rw] Retrain Link. Not applicable and reserved for EP. | |
uint8_t | linkDisable |
[rw] Disables the link by directing the LTSSM to the Disabled state when set. | |
uint8_t | rcb |
[rw] Read Completion Boundary. | |
uint8_t | activeLinkPm |
[rw] Active State Link Power Management Control |
Specification of the Link Status and Control Register.
This register may be used for both endpoint and root complex modes.
[rw] Active State Link Power Management Control
0 = Disabled.
1h = L0s entry enabled.
2h = L1 entry enabled.
3h = L0s and L1 entry enabled.
Field size: 2 bits
[rw] Enable Clock Power Management.
Field size: 1 bit
[rw] Common Clock Configuration.
0 = Indicates that this device and the device at the opposite end of the link are operating with separate reference clock sources.
1 = Indicates that this device and the device at the opposite end of the link are operating with a common clock source.
Field size: 1 bit
uint8_t pcieLinkStatCtrlReg_s::dllActive |
[rw] Data Link Layer Active
This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1 to indicate the DL_Active state, 0 otherwise.
Field size: 1 bit
uint8_t pcieLinkStatCtrlReg_s::extSync |
[rw] Extended Synchronization.
Field size: 1 bit
[rw] Hardware Autonomous Width Disable. Not supported and hardwired to zero.
Field size: 1 bit
[rw] Link Autonomous Bandwidth Interrupt Enable. Not applicable and is reserved for EP
Field size: 1 bit
[rw] Link Bandwidth Management Interrupt Enable. Not applicable and is reserved for EP.
Field size: 1 bit
[rw] Link Bandwidth Management Status.
This bit is Set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status:
This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change.
Not applicable and reserved for EP.
Field size: 1 bit
[rw] Link Autonomous Bandwidth Status.
This bit is Set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation. This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change.
Not applicable and reserved for EP.
Field size: 1 bit
[rw] Disables the link by directing the LTSSM to the Disabled state when set.
Field size: 1 bit
uint8_t pcieLinkStatCtrlReg_s::linkSpeed |
[rw] Link Speed. Set automatically by hardware after link initialization.
Field size: 4 bits
[rw] Link Training. Not applicable to EP.
Field size: 1 bit
[rw] Negotiated Link Width. Set automatically by hardware after link initialization.
Field size: 6 bits
uint32_t pcieLinkStatCtrlReg_s::raw |
[ro] Raw image of register on read; actual value on write
uint8_t pcieLinkStatCtrlReg_s::rcb |
[rw] Read Completion Boundary.
0 = 64 bytes
1 = 128 bytes
Field size: 1 bit
[rw] Retrain Link. Not applicable and reserved for EP.
Field size: 1 bit
[rw] Slot Clock Configuration. Writable from internal bus interface.
This bit indicates that the component uses the same physical reference clock that the platform provides on the connector.
Field size: 1 bit
uint8_t pcieLinkStatCtrlReg_s::undef |
[rw] Undefined for PCI Express.
Field size: 1 bit