Data Fields
Qmss_InitCfg Struct Reference

QMSS configuration structure. More...

#include <qmss_qm.h>

Data Fields

uint32_t linkingRAM0Base
uint32_t linkingRAM0Size
uint32_t linkingRAM1Base
uint32_t maxDescNum
Qmss_PdspCfg pdspFirmware [QMSS_MAX_PDSP]
uint32_t qmssHwStatus
Qmss_Mode mode
Qmss_LinkingRAM splitLinkingRAMs [QMSS_MAX_QMGR_GROUPS-1]

Detailed Description

QMSS configuration structure.

The linkingRAMs are specified in two parts. This allows backwards compatibility to those * who memset() this structure to 0. It will default to JOINT mode so existing code runs without modification since it will be able to see all queue types in the system.

In JOINT mode: only linkingRAM0Base, linkingRAM0Size, and linkingRAM1Base are used to configure all QM groups simutaneously.

In SPLIT mode: linkingRAM0Base, linkingRAM0Size, and linkingRAM1Base are used to configure the first QM group. The subsequent groups are configured using splitLinkingRAMs and


Field Documentation

Base address of Linking RAM 0. LLD will configure linking RAM0 address to internal linking RAM address if a value of zero is specified.

Linking RAM 0 Size. LLD will configure linking RAM0 size to maximum internal linking RAM size if a value of zero is specified

Base address of Linking RAM 1. Depends on RAM 0 Size and total number of descriptors. If linkingRAM1Base is zero then linkingRAM0Size must be large enough to store all descriptors in the system

Maximum number of descriptors in the system. Should be equal to less than the RAM0+RAM1 size

Allocation mode

PDSP firmware to download. If the firmware pointer is NULL, LLD will not download the firmware

Status of QMSS HW. Set this to QMSS_HW_INIT_COMPLETE in case Initialization is already complete. Setting this flag will bypass any QMSS Hardware initialization

Linking RAMs for other QM groups when in SPLIT mode


The documentation for this struct was generated from the following file:

Copyright 2014, Texas Instruments Incorporated