Data Fields
Tcp3d_Instance Struct Reference

TCP3D Driver instance structure. More...

#include <tcp3d_drv.h>

Data Fields

uint8_t instNum
volatile Tcp3d_State state
uint8_t mode
uint16_t doubleBuffer
volatile uint8_t pingStop
volatile uint8_t pongStop
uint8_t startFlag
uint8_t coreId
int32_t pingFreeCnt
int32_t pongFreeCnt
uint32_t maxCodeBlocks
uint32_t nextCodeBlockIndex
EDMA3_DRV_PaRAMRegs * pseudoParamBufPtr
uint32_t notificationEventNum
void * cpIntc0RegsBase
EDMA3_DRV_Handle edmaHnd
uint32_t edmaRegionId
uint32_t pingCh [TCP3D_DRV_MAX_CH_PER_PATH]
uint32_t pongCh [TCP3D_DRV_MAX_CH_PER_PATH]
uint32_t pingChParamAddr [TCP3D_DRV_MAX_CH_PER_PATH]
uint32_t pongChParamAddr [TCP3D_DRV_MAX_CH_PER_PATH]
uint32_t pingLinkCh [TCP3D_DRV_MAX_LINK_CH >>1]
uint32_t pongLinkCh [TCP3D_DRV_MAX_LINK_CH >>1]
uint32_t pingLinkChParamAddr [TCP3D_DRV_MAX_LINK_CH >>1]
uint32_t pongLinkChParamAddr [TCP3D_DRV_MAX_LINK_CH >>1]
uint32_t l2pChMaskPing
uint32_t l2pChMaskPong
uint32_t pauseChMaskPing
uint32_t pauseChMaskPong
CSL_TPCC_ShadowRegs * tpccShadowRegs
uint32_t * intEnClrReg [2]
uint32_t * intEnSetReg [2]
uint32_t * clrIntPendReg [2]
uint32_t * intPendReg [2]
uint8_t constantOne
Tcp3d_State pauseState

Detailed Description

TCP3D Driver instance structure.


Field Documentation

Register address of TPCC_ICR used for clearing the pending IPR bits

variable set to 1 at init time and used by PAUSE channels

CPU/DSP core ID on which this instance of driver is running

CP_INTC0 register overlay base address. This is expected of type CSL_CPINTC_RegsOvly.

Double Buffer mode enable/disable

EDMA3_DRV_Handle Tcp3d_Instance::edmaHnd

EDMA3 LLD Driver Handle

EDMA shadow region number

TCP3D Peripheral instance number

Register address of TPCC_IECR used for clearing (diable) the IER bits

Register address of TPCC_IESR used for setting (enable) the IER bits

Register address of TPCC_IPR used for checking pending interrupts

bit masks used for controlling interrupt generation by EDMA CC L2P Channel Mask for PING

L2P Channel Mask for PONG

Gives the Maximum number of code blocks that can be enqueued using the driver. This value is set during the init.

Driver operating Mode for the given instance

Gives the next code block index for enqueue into the input list.

CP_INTC0 input event number used for the output notification. Driver uses this value to write (using EDMA) into the STATUS_SET_INDEX_REG during run-time to cause system event/interrupt.

REVT Channel Mask for PING

REVT Channel Mask for PING

variable set to TCP3D_DRV_STATE_PAUSE and used by PAUSE channels

Ping channels stored here

Physical PaRAM addresses of the Ping channels

Gives the number of free entries available in the input ping list for enqueue. This flag is decremented when a code block is enqueued into the ping list. It's value is updated in the start funciton.

Link channels for Ping path

Link channel PaRAM address for Ping path

volatile uint8_t Tcp3d_Instance::pingStop

If true, PING path is stopped

Pong channels stored here

Physical PaRAM addresses of the Pong channels

Gives the number of free entries available in the input pong list for enqueue. This flag is decremented when a code block is enqueued into the pong list. It's value is updated in the start funciton.

Link channels for Pong path

Link channel PaRAM address for Pong path

volatile uint8_t Tcp3d_Instance::pongStop

If true, PONG path is stopped

EDMA3_DRV_PaRAMRegs* Tcp3d_Instance::pseudoParamBufPtr

Pointer to the pseudo PaRAM buffer array base.

TCP3D driver start mode flag. Set to NULL during init to disable the auto start function call from enqueue funciton until application initiates.

Variable to keep the driver state

CSL_TPCC_ShadowRegs* Tcp3d_Instance::tpccShadowRegs

EDMA shadow registers base address used during run-time


The documentation for this struct was generated from the following file:

Copyright 2014, Texas Instruments Incorporated